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[SOLVED] unequal transition time for the pins connected to one net

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r1caw ex ua6bqg

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Hi all!

After place-and-route in the Synopsys ICC I have timing report for some worst path. For example, it looks similar like this:

Name.........Reference.....Type..... Cap........Trans ...others results...
/DFF/CP.......DFF12LVT.......in.......0.0013....0.100
/DFF/Q........DFF12LVT......out......0.0000....0.038
/n46................net.....................0.0645
/AND/A2.......AND4LVT.......in.......0.0019....0.107
/AND/Z.........AND4LVT......out......0.0000....0.039
/n22................................net.....0.0035
/OR/A2.........AND4LVT........in......0.0010....0.039
/OR/Z...........AND4LVT.......out.....0.0000....0.032

So, the question is: why in some cases output and input transition time for two nets (out and in) connected to the similar net are equal, and in some cases they are unequal? I thought for any source and sink pins connected together transition time must be equal, but now I am little bit confused.
Thank you!
 

I can't understand this question. What is a 'net connected to a similar net'?

My guess is you are seeing different delays on the same net because the transition changes from L->H to H->L
 

Hi, thank you for your answer!
Of course I mean the situation when two ports (out of one cell and input of another cell) are connected to the same net (i.e. connected together). So, source drives capacitance of this net (which includes wires capacitance, input capacitance etc) and thus transition time on this net must be same for input and output ports in the timing report. But they are different as you can see, and I want to understand why.
 

Within an FPGA, multiple destination endpoints from a single sourcepoint are not directly connected. The routes have to go through LUTs or CFG blocks to change "direction" to a different part of the chip. Thus the difference in propagation delay.

For actual input and output ports there is not only the different routes mentioned above but there is a difference in propagation time due to pin to pad timing differences: this is the timing delta due to different micro trace wire between the pin on the FPGA package that you can physically see, and the pad on the actual die of FPGA silicon. I know Xilinx and Microsemi document these numbers in a spreadsheet. The difference is usually in the 10s of picoseconds.

Hopefully I understood your question correctly!
 

Thank you for your answer!
Actually, I posted netlist from Synopsys ICC which performs place and route for ASICs and no related with FPGA. So, in this example, this in\out ports are really directly connected.
 

ua6bqg said:
Hi, thank you for your answer!
Of course I mean the situation when two ports (out of one cell and input of another cell) are connected to the same net (i.e. connected together). So, source drives capacitance of this net (which includes wires capacitance, input capacitance etc) and thus transition time on this net must be same for input and output ports in the timing report. But they are different as you can see, and I want to understand why.
Click to expand...

Actually I can't see. Your post is very confusing with that partial timing report. If you want further help, please show a diagram of sorts and clearly state what you expect to see versus what you are seeing.
 

Ok, thank you!

That's what I see in the report from Synopsys ICC:

Name.........Reference.....Type..... Cap........Trans ...others results...
/DFF/CP.......DFF12LVT.......in.......0.0013....0.100
/DFF/Q........DFF12LVT......out......0.0000....0.038
/n46................net.....................0.0645
/AND/A2.......AND4LVT.......in.......0.0019....0.107
/AND/Z.........AND4LVT......out......0.0000....0.039
/n22................................net.....0.0035
/OR/A2.........AND4LVT........in......0.0010....0.039
/OR/Z...........AND4LVT.......out.....0.0000....0.032

For example, the Trans time for DFF/Q and AND/A2 connected to the same net /n46 is different (0.038 and 0.107).

And what I expect to see (for example):

Name.........Reference.....Type..... Cap........Trans ...others results...
/DFF/CP.......DFF12LVT.......in.......0.0013....0.100
/DFF/Q........DFF12LVT......out......0.0000....0.107
/n46................net.....................0.0645
/AND/A2.......AND4LVT.......in.......0.0019....0.107
/AND/Z.........AND4LVT......out......0.0000....0.039
/n22................................net.....0.0035
/OR/A2.........AND4LVT........in......0.0010....0.039
/OR/Z...........AND4LVT.......out.....0.0000....0.032

Here, the the Trans time for DFF/Q and AND/A2 connected to the same net /n46 is same (0.107), and as I can understand, it is physically correct.

So, the question is why in the ICC report I see unequal transition time for out and input (they have the same Rise direction).
 

Bigger wire (net) length -> bigger difference in transition time on source and destintion pins of the net. Due to the resistance of wire.
 
ua6bqg said:
Ok, thank you!

That's what I see in the report from Synopsys ICC:

Name.........Reference.....Type..... Cap........Trans ...others results...
/DFF/CP.......DFF12LVT.......in.......0.0013....0.100
/DFF/Q........DFF12LVT......out......0.0000....0.038
/n46................net.....................0.0645
/AND/A2.......AND4LVT.......in.......0.0019....0.107
/AND/Z.........AND4LVT......out......0.0000....0.039
/n22................................net.....0.0035
/OR/A2.........AND4LVT........in......0.0010....0.039
/OR/Z...........AND4LVT.......out.....0.0000....0.032

For example, the Trans time for DFF/Q and AND/A2 connected to the same net /n46 is different (0.038 and 0.107).

And what I expect to see (for example):

Name.........Reference.....Type..... Cap........Trans ...others results...
/DFF/CP.......DFF12LVT.......in.......0.0013....0.100
/DFF/Q........DFF12LVT......out......0.0000....0.107
/n46................net.....................0.0645
/AND/A2.......AND4LVT.......in.......0.0019....0.107
/AND/Z.........AND4LVT......out......0.0000....0.039
/n22................................net.....0.0035
/OR/A2.........AND4LVT........in......0.0010....0.039
/OR/Z...........AND4LVT.......out.....0.0000....0.032

Here, the the Trans time for DFF/Q and AND/A2 connected to the same net /n46 is same (0.107), and as I can understand, it is physically correct.

So, the question is why in the ICC report I see unequal transition time for out and input (they have the same Rise direction).
Click to expand...

check the documentation on what the meaning of transition time is for different 'types of nets', I am sure one calculation is not taking some cap into account or something like that. Unfortunately I am not familiar with ICC to help you with that.
 

ua6bqg said:
Thank you, it sounds realistic.
Click to expand...

transient output used cad tool also depend on step size and accuracy those are depend on design and user.
for small design and small time these fact are not more important then big & complicated design.
 

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