Conditional CDC : Timing and CDC violations

Please refer to the circuit diagram. Config is a configuration register bit which is quasi-static (set at boot and doesn't change dynamically during operation of chip).
When config = 0 clk_0 and clk_1 are asynchronous while when config = 1 clk_0 and clk_1 are synchronous.

[1] Timing : What is the best way of timing this circuit? Is is ok to define these two clocks as synchronous for synthesis and timing ? Even when config=0, tool will be optimizing/timing path between FF1 and FF2.

[2] CDC : Is there a CDC problem in this design for path between FF1 and FF2 ? Does config being quasi-static means there wont be any glitch propagation and meta-stability problem ?

[3] If clk_0 and clk_1 are defined as synchronous will the CDC miss any other clock crossing paths ?

[4] Any other potential problems with this design I should worry about ?

Thanks !