Matching improves for bigger or smaller layouts?

Given an opamp layout, the matching is better for smaller or bigger layout? Considering to have the exact circuit in two different sizes, bigger and smaller, the matching is better for which one of the two implementation? And why?

You never have the "exact same circuit in two different
sizes". Parasitics, as a minimum, differ. But you have to
presume that a size difference is a result of some layout
differences.

Matching outcome depends on "stuff".

If your matching is dominated by gradients in the silicon
then smaller is better. But even there, thermal gradient
may be reduced by larger size while litho gradient has
more dX, dY run to develop. Random mismatch is not
affected by size (other than, a weak analysis may not
distinguish between random and systematic elements
of mismatch).

If you got smaller size by getting rid of dummies and
centroiding layout styles, then smaller is likely to be
worse. If you got larger by adding them (properly),
larger ought to be better - not the mean, but the
span of the distribution.

Also, the device mismatch scales roughly as 1/sqrt(Area), so if your circuit is limited by device mismatch, the bigger device area is better.
And, if mismatch is affected by parasitic capacitance mismatch, the larger the design elements, the smaller the effect of parasitic capacitance mismatch, the better.
Also, doing a proper shielding of sensitive elements (such as capacitors in a capacitor bank of SAR ADC) will definitely help - making the area larger.
If it is parasitic resistance limited mismatch - such as difference in resistances and IR drop from power/ground net ports to differential pair "matched" transistors' source of drain pins - it all depends on the quality of the layout (and your ability to detect and debug these mismatches), either larger size or smaller size layout may be better. In general enabling resistance / IR drop matching of large area devices is more complex, and might benefit greatly from using proper software tools for analysis.

As dick_freebird said, if mismatch is limited by large-scale gradients (on-chip temperature, process variation over chip area, etc.) - the smaller size, the better.