shashi106
Newbie level 4
Hello,
I am performing simulation of a complex cmos circuit in Pyxis,Mentor Graphics tool 130 nm technology and I want to know what is the acceptable output voltage level for low and high logic states in 130 nm technology?
Please help.
Thanks in Advance.
I am performing simulation of a complex cmos circuit in Pyxis,Mentor Graphics tool 130 nm technology and I want to know what is the acceptable output voltage level for low and high logic states in 130 nm technology?
Please help.
Thanks in Advance.