dpaul
Advanced Member level 5
Hi,
I have a generic of type standard logic passed down from top-level to module level.
Based on a '1' value of that generic, I want declare a certain set of signals. If the generic value is '0', I want to declared another set of signals.
I think I cannot use generate.
What is the best way to do it?
IDE - Vivado 2017.2
Regards.
---------------------------------------------------------------
Update> Thinking about an alternative like....is it the best approach?
I have a generic of type standard logic passed down from top-level to module level.
Based on a '1' value of that generic, I want declare a certain set of signals. If the generic value is '0', I want to declared another set of signals.
I think I cannot use generate.
What is the best way to do it?
IDE - Vivado 2017.2
Regards.
---------------------------------------------------------------
Update> Thinking about an alternative like....is it the best approach?
Code:
entity my_entity is
generic(
GENERIC_VAL : std_logic := '0'
);
port (
.
.
);
end my_entity;
architecture my_entity_arc of my_entity is
signal a : std_logic; --
signal b : std_logic; --
signal c : std_logic; -- common signal
begin
.
.
use_gen : if GENERIC_VAL='0' generate
c <= a;
else generate
c <= b;
end generate use_gen;
.
.
end my_entity_arc;
Last edited: