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GENUS: keeping multiple instances of the same module

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digitalo

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Hi all,

this has been asked and answered a while back for an older version of RC:
https://www.edaboard.com/showthread.php?t=195042

I have the same problem, but the old solution ported to GENUS no longer works for me. To be more specific:
I have a Verilog module "channel" that has several instances in "all_channels". I tried
set_db module:all_channels/channel .minimize_uniquify true
set_db module:all_channels/channel .ungroup_ok false
in various combinations. The results vary, but I never get what I want.

The goal is to retain exactly one channel module definition with multiple instances to put into the hierarchical flow of INNOVUS. But I either get channel, channel_1, etc. modules, or channel for the first instance and the logic of the other channels flattened into all_channels.

How do I have to use GENUS to produce output that is suitable for the INNOVUS hierarchical flow?

My current workaround is to first synthesize channel, then all_channels while channel is just visible as a black box, then merge the outputs. This somehow works, but has several problems, moving the timing constraints between GENUS and INNOVUS probably being the biggest one.

Thanks,
digitalo
 

have you tried set_db auto_ungroup none ? this will not allow any ungrouping and should preserve the hierarchy.
 

have you tried set_db auto_ungroup none ? this will not allow any ungrouping and should preserve the hierarchy.

No, I had not tried this. But is doesn't help anyway. It gets me back to channel, channel_1, channel_2 ….
(I have tried set_db root: .auto_ungroup none).
 

No, I had not tried this. But is doesn't help anyway. It gets me back to channel, channel_1, channel_2 ….
(I have tried set_db root: .auto_ungroup none).

Can you draw your logical hierarchy and the implementation hierarchy? I am confused.
 

Can you draw your logical hierarchy and the implementation hierarchy? I am confused.

In the input file I have

for( i = 0; i < num_channels; i = i + 1 )
begin : gen_one_channel
channel channel_I(…).
end

After GENUS, I have
channel \gen_one_channel[0].channel_I(…);
channel_1 \gen_one_channel[1].channel_I(…);
channel_2 \gen_one_channel[2].channel_I(…);

But I need
channel \gen_one_channel[0].channel_I(…);
channel \gen_one_channel[1].channel_I(…);
channel \gen_one_channel[2].channel_I(…);
to make it useful in the INNOVUS partition flow.
 

have a look at the documentation for the naming style and separator, it might solve your problem. search for hdl_generate_index_style and hdl_generate_separator
 

have a look at the documentation for the naming style and separator, it might solve your problem. search for hdl_generate_index_style and hdl_generate_separator

These settings merely change the names to another set of unique names per instance.
They do not affect whether the module is cloned or not.
 

you can use design compiler for synthesis.
very good tool.

how is this remotely relevant?

- - - Updated - - -

OP, as much as you don't want to hear it, what you are trying to do is not the standard behavior of the tool. Our job as users of these EDA tools is to find alternatives... and for me it seems a script could easily do what you want.

Said script could be a tcl/shell script, using sed to find and replace modules names. It could also be a tcl script inside genus that would automatically rename modules for you. Both alternatives seem to be possible to me. Good luck.
 

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