RickyRuf
Newbie level 2
Hello everybody,
i'm using an FPGA 10M25SCE144I7G and i found this problem: the output xxx in pin location 27 is too close to PLL clock input pin in pin location 26.
Is it possible to disregard this problem? Right now the pin 27 is a clock enable pin used for a crystal that gives the clock for the PLL, so this pin it is always fixed at a certain logic level and it is not dangerous for the PLL.
Thank you for your attention
i'm using an FPGA 10M25SCE144I7G and i found this problem: the output xxx in pin location 27 is too close to PLL clock input pin in pin location 26.
Is it possible to disregard this problem? Right now the pin 27 is a clock enable pin used for a crystal that gives the clock for the PLL, so this pin it is always fixed at a certain logic level and it is not dangerous for the PLL.
Thank you for your attention