Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Design Compiler Warning (OPT-150) (OPT-314) break a timing loop, can anyone help me?

Status
Not open for further replies.

ilv32312

Newbie level 1
Joined
Jul 26, 2017
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
17
Design Compiler Warning (OPT-150)(OPT-314) break a timing loop,anyone help me?

This is my Phase Detector circuit & RTL code & RTL simulation
003.png001.png002.png0000.png

Then I used "Design Compiler",Enter the instruction:write_sdf -version 2.1 -context Verilog"./gl.sdf"
The following warning appears
005.png


Then I Enter the instruction: set_disable_timing ,as shown below
00088.png

then finish to produce gate-level.v
but my gate-level simulation ,The output signal disappears
00009.png
this is my gate-level simulation

Who can tell me where to do wrong? Thanks
 

Re: Design Compiler Warning (OPT-150)(OPT-314) break a timing loop,anyone help me?

So many issues.
Why would you do this in RTL/digital logic is beyond me. This is not a good idea.
You are blindly using set_disable_timing on all pins? Why? What are you trying to achieve?
Why would clock stop ticking on your gate level simulation? Did you even notice that the most basic signal of all is missing?
 

Re: Design Compiler Warning (OPT-150)(OPT-314) break a timing loop,anyone help me?

Why would clock stop ticking on your gate level simulation? Did you even notice that the most basic signal of all is missing?
CLK is not a clock it is an output of their circuit.
 

Re: Design Compiler Warning (OPT-150)(OPT-314) break a timing loop,anyone help me?

CLK is not a clock it is an output of their circuit.

Ah, yes, I see it now. It's an OR between D and U, in theory.

What is the content of gl.v?
 

Re: Design Compiler Warning (OPT-150)(OPT-314) break a timing loop,anyone help me?

Looking at the circuit, I suspect the FFs are outputting X for both Qref and Qfb starting from time 0, as the NAND gate producing PDrst has X inputs it produces an X output, which in turn causes the FF models to ignore the fref and ffb clocks and produce Xs on the FF outputs again.

The original RTL simulation works because the if (!reset) in the FF code will be false as reset is X which will always mean the else is taken so Q gets assigned the D input. The model for the gate level netlist doesn't behave this way as it likely checks for X's on all the inputs and assigns Q <= 1'bx;

X's on resets can result in strange behaviors vs gate level code.

- - - Updated - - -

Realistically the gate level netlist will likely work as the FFs will power up either 1 or 0 and the circuit will have a valid logic input to the !RST input. The X is a simulation artifact that results in the simulation misbehavior that won't occur in the real world.

I'd suggest adding an initial statement to the test bench and assign both FF outputs with 0, the 0's will be overridden once the first ffb and fref arrive.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top