ilv32312
Newbie level 1
Design Compiler Warning (OPT-150)(OPT-314) break a timing loop,anyone help me?
This is my Phase Detector circuit & RTL code & RTL simulation
Then I used "Design Compiler",Enter the instruction:write_sdf -version 2.1 -context Verilog"./gl.sdf"
The following warning appears
Then I Enter the instruction: set_disable_timing ,as shown below
then finish to produce gate-level.v
but my gate-level simulation ,The output signal disappears
this is my gate-level simulation
Who can tell me where to do wrong? Thanks
This is my Phase Detector circuit & RTL code & RTL simulation
Then I used "Design Compiler",Enter the instruction:write_sdf -version 2.1 -context Verilog"./gl.sdf"
The following warning appears
Then I Enter the instruction: set_disable_timing ,as shown below
then finish to produce gate-level.v
but my gate-level simulation ,The output signal disappears
this is my gate-level simulation
Who can tell me where to do wrong? Thanks