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Assume it is asynchronous reset:
At rising edge of CLK ....
* If RST is considered = LOW, then it may work
* If RST is considered = HIGH, then the output will be cleared, independent of D state. So the output never becomes HIGH.
Setup and hold times may clarify behaviour for your design, but with another design the behaviour may be different.
Ok that's helpful. So you are trying to say that if I have an active low RST then it might work. So the hold time would pass without an issue but the setup time might be of a real concern. But if I hold the D constant ; my timing would go clean.
This is so unintelligent and against all rules of digital design. Q must remain stable for the duration of the entire clock cycle, otherwise timing is a nightmare. Operating on two clock edges is not something desirable.
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