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readmemh is not loading file into simulator

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Mohitkalra0207

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I am doing image processing and for that I have converted my image to text file using matlab and now I want to load this file containing text for the image in model sim using the following code


Code Verilog - [expand]
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module iprocess();
reg [2:0]mem[2:0];
initial 
begin
$readmemh ("C:\Users\mohit kalra\Documents\image_process\New_Text_Document0.txt",mem);
end
endmodule



but I am getting that it is not loading any file and hence in mem register I am getting "XX " repeatedly
Please provide me the wayout of this problem.
I have tried the code on Xilinx as well but again the same result.
 

what does the New_Text_Document0.txt file look like?

I've tried this in vivado and the code works as long at the file is located in the correct place and has white space separated entries between 0-7 (8-f are truncated to 3-bits).

- - - Updated - - -

Ah, I see the problem now, my test code worked because I used / instead of \.

Change your directory separator to / Modelsim uses unix style directory separators for files otherwise you have to use \\ for a single \.
 

my text file looks like:
a
b
c
d
e
and this text file is stored in directory shown by tcl command 'pwd' -C:/Users/mohit kalra/AppData/Roaming/Xilinx/Vivado
Please suggest am I write?
 

File will give you 2, 3, 4,... as your mem array is only 3-bits wide, other than that the file will work as written. According to your two posts the locations are different, they need to be pointed to the same location.
 

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