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VHDL equivalent of Verilog code

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hareeshP

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Hi,
please anyone post the vhdl equivalent of the following verilog code,
Code Verilog - [expand]
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always @(posedge ifc_clk or negedge pon_rst_n or posedge rst_hold_f)
[/syntax]
Thanks
 

difficult without the rest of the code, but probably something like this:

Code VHDL - [expand]
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process(ifc_clk, pon_rst_n, rst_hold_f)
begin
  if pon_rst_n = '0' then
  -- reset 1
  elsif rst_hold_f = '1' then
  --reset 2
  elsif rising_edge(ifc_clk) then
    --synchronous code
 end if;
end process;


Pretty basic stuff...
 
the code is given below
Code Verilog - [expand]
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always @(posedge ifc_clk or negedge pon_rst_n or posedge rst_hold_f)
begin
    if(!pon_rst_n )
    begin
        x1<= 0;
        x2 <= 0;
        x3<= 0;
        x4 <= 0;
        x5<= 0;
        x6 <= 0;        
        x7 <= 0;
        x8<= 0;
        end


- - - Updated - - -

In this code if anyone of the signal (ifc_clk, pon_rst_n, pon_rst_n) changes, the rest of the code will executes
is that right?
 

This cant be the whole code, as this just shows a reset.
Your assertion is partially correct, but it will only trigger on the edges specified in the eventControl statement ( the @ ).
 

In this code if anyone of the signal (ifc_clk, pon_rst_n, pon_rst_n) changes, the rest of the code will executes is that right?
Click to expand...

Yes, that's how sensitivity list works.
 

TrickyDicky said:
This cant be the whole code, as this just shows a reset.
Your assertion is partially correct, but it will only trigger on the edges specified in the eventControl statement ( the @ ).
Click to expand...
You are right, this is just a part of the code. and i want the equivalent in vhdl .

- - - Updated - - -

TrickyDicky said:
difficult without the rest of the code, but probably something like this:

Code VHDL - [expand]
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process(ifc_clk, pon_rst_n, rst_hold_f)
begin
  if pon_rst_n = '0' then
 
  elsif rst_hold_f = '1' then
 
  elsif rising_edge(ifc_clk) then
 
 end if;
end process;


Pretty basic stuff...
Click to expand...

What happens if i put
Code VHDL - [expand]
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if rising_edge(ifc_clk) then
 
  elsif pon_rst_n = '0' then
 
  elsif  rst_hold_f = '1' then
 
 end if;
end process;
 

Then you have made an asynchronous reset from the verilog code into a synchronous one in VHDL.
 

TrickyDicky said:
Then you have made an asynchronous reset from the verilog code into a synchronous one in VHDL.
Click to expand...
That's all i want. but when i simulate the below code it is showing some error
Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity t1024_1 is 
port(clk,pon_rst_n: in std_logic;  
        ifc: out std_logic);
end t1024_1;
architecture behav of t1024_1 is
begin
    process(clk,pon_rst_n )
begin
  if (rising_edge(clk)) then 
    elsif pon_rst_n = '1' then
     ifc<= '1';
     else 
     ifc<= '0';
 end if;
end process;
end behav;


Error (10818): Can't infer register for "ifc" at test4.vhd(12) because it does not hold its value outside the clock edge.
 

I would prefer to see the original Verilog code to check, if it's synthesizable at all. Otherwise, it would be pointless to convert it to VHDL.

Take care that there can be only one truely edge sensitive condition in the always block. It's clear so far that pon_rst is an asynchronous (level sensitive) condition, but because you didn't show the other code, the nature of rst_hold is unclear.

Error (10818): Can't infer register for "ifc" at test4.vhd(12) because it does not hold its value outside the clock edge.
Click to expand...
A typical non-synthesizable construct. Try to follow the template suggested by TrickyDicky: Asynchronous conditions first else rising_edge()...
 

please anyone give me the vhdl equivalent of above code.
 

FvM said:
Take care that there can be only one truely edge sensitive condition in the always block. It's clear so far that pon_rst is an asynchronous (level sensitive) condition
Click to expand...
I know that only one truely edge sensitive condition can be implemented in an always block/process, but why ? One can have multiple clocks.. how do you manage a code which needs to handle multiple clocks?
 

CataM said:
I know that only one truely edge sensitive condition can be implemented in an always block/process, but why ? One can have multiple clocks.. how do you manage a code which needs to handle multiple clocks?
Click to expand...

This is just a limitation of FPGA hardware - Registers only have a single clock input. In Asic, multiple clocks per register may be possible if you're using technology that supports it.
In a design with multiple clock domains, no registers ever need multiple clocks.
 
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hareeshP said:
please anyone give me the vhdl equivalent of above code.
Click to expand...

You mean for this code?
hareeshP said:
the code is given below
Code Verilog - [expand]
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always @(posedge ifc_clk or negedge pon_rst_n or posedge rst_hold_f)
begin
    if(!pon_rst_n )
    begin
        x1<= 0;
        x2 <= 0;
        x3<= 0;
        x4 <= 0;
        x5<= 0;
        x6 <= 0;        
        x7 <= 0;
        x8<= 0;
        end


In this code if anyone of the signal (ifc_clk, pon_rst_n, pon_rst_n) changes, the rest of the code will executes
is that right?
Click to expand...

Code VHDL - [expand]
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process (ifc_clk, pon_rst_n, rst_hold_f)
begin
  if (pon_rst_n = '0') then
    x1 <= '0';
    x2 <= '0';
    x3 <= '0';
    x4 <= '0';
    x5 <= '0';
    x6 <= '0';
    x7 <= '0';
    x8 <= '0';
-- you didn't specify the rst_hold_f in the above code, so I'm not including it here
-- basically you didn't ask a good question
  elsif rising_edge(ifc_clk) then
    -- synchronous code
  end if;
end process;
 

This is just a limitation of FPGA hardware - Registers only have a single clock input. In Asic, multiple clocks per register may be possible if you're using technology that supports it.
In a design with multiple clock domains, no registers ever need multiple clocks.
Click to expand...
There's no commonly agreed syntax to model a register with multiple clocks in Verilog. In the usual Verilog register modeling template, there can be only one final else statement which "specifies the synchronous logic part of the design" (IEEE 1364.1-2002).

Although 1364.1 isn't part of the recent IEEE 1800 System Verilog standard, it hasn't been replaced by a new RTL synthesis specification. Please correct me, if you know a commonly agreed Verilog Syntax for registers with multiple clocks.

In more practical regard, I understand that the thread is about FPGA synthesis, so registers with multiple clocks aren't an option.
 
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