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need help for verilog code

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Adnan86

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Hi,
I Wrote this code, for signed Multipliction. but i have some error:
Code:
module FP_mult #(parameter M=4, N=11)(
	input   				clk,
	input   				rst,
	input  [M+N : 0]	multiplicand,
	input  [M+N : 0]	multiplier,
	output [2*(M+N)+1 : 0]   product);
	reg 	 [2*(M+N)+1 : 0]   partial_mult;
	
	reg 	 [4:0]  				num;
	reg 	  					flag;
	
	always @ (posedge clk , posedge rst)	begin
		
		if (rst) begin
		partial_mult <= 0;
		num <= 0;
		flag <= 0;
		end
		else if ((num <= M+N) && (flag != 1'b1)) begin
			partial_mult <= partial_mult + (({16{multiplicand[M+N]},multiplicand}) << num);
			num <= num + 1'b1;
		end
		else if ((num == M+N+ 1'b1) && (flag != 1'b1)) begin
			if (multiplicand[M+N]) begin
			partial_mult <= partial_mult + (~({16{multiplicand[M+N]},multiplicand} << num)) + 1'b1;
			flag <= 1'b1;
			end
			
			else
			flag <= 1'b1;
			end	
	end
	assign product = partial_mult;
endmodule
Error happend for this two line at first :
Code:
partial_mult <= partial_mult + (~({16{multiplicand[M+N]},multiplicand} << num)) + 1'b1;
error :
syntax and it said unexpect "," also need "}"
how I can solve it. and also any advice for doing better to write this case.
Thanks aand I will appreciat for your help.
 

You need another set of {} around the 16 {xxxx}, i.e. { {16 {xxxxx}}, yyyyy }
 
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