VerilogA_Novice
Newbie level 1
Hello, I have a difficulty in making verilog-A Model for short interval input event.
For example, Here is an and gate.
1. Propagation Delay=5ns
If there is an Input signal '1' when t=0~4ns,
Output must be 0 for all time because input signal '1' interval is shorter than the propagation delay(5ns)
but my model displays an output t=5ns~9ns
How can I make Verilog-A Model that have an immunity for short interval input ?
Help me TT
For example, Here is an and gate.
1. Propagation Delay=5ns
If there is an Input signal '1' when t=0~4ns,
Output must be 0 for all time because input signal '1' interval is shorter than the propagation delay(5ns)
but my model displays an output t=5ns~9ns
How can I make Verilog-A Model that have an immunity for short interval input ?
Help me TT
