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    VHDL Register transferring.

    hi,
    please anyone tell me
    how to transfer the bits of one register to another register in vhdl?

    •   Alt19th July 2017, 13:28

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    Re: VHDL Register transferring.

    Code VHDL - [expand]
    1
    
    reg2 <= reg1;



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    Re: VHDL Register transferring.

    but i want to transfer the first bit of reg1 to first bit of reg2..



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    Re: VHDL Register transferring.

    Code VHDL - [expand]
    1
    
    reg2(0) <= reg1(0);   -- assuming reg1/2 are arrays where 0th element is first bit



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    Re: VHDL Register transferring.

    Code VHDL - [expand]
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    library ieee;
    use ieee.std_logic_1164.all;
    entity test3 is
    port(clk: in std_logic; 
            ifc_a: out std_logic_vector(1 downto 0));
    end test3;
    architecture modu of test3 is
        signal ifc_dout: std_logic_vector(1 downto 0);
    begin
        process(clk) then
        begin
            if(rising_edge(clk)) then
                ifc_a(0)<=ifc_dout(0);
                ifc_a(1)<=ifc_dout(1);
            end if;
        end process;
    end modu;



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    Re: VHDL Register transferring.

    how to transfer the bits of one register to another register in vhdl?
    but i want to transfer the first bit of reg1 to first bit of reg2..
    You should figure out the question before you ask.

    Code:
    ifc_a(0)<=ifc_dout(0);
    ifc_a(1)<=ifc_dout(1);
    is just the same as

    Code:
    ifc_a<=ifc_dout;



    •   Alt19th July 2017, 15:16

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    Re: VHDL Register transferring.

    reg1(2:3) <= reg2(3:4);
    is this valid in vhdl?



    •   Alt1st August 2017, 11:07

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    Re: VHDL Register transferring.

    Quote Originally Posted by hareeshP View Post
    reg1(2:3) <= reg2(3:4);
    is this valid in vhdl?
    No, it is not.


    1 members found this post helpful.

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    Re: VHDL Register transferring.

    Quote Originally Posted by TrickyDicky View Post
    No, it is not.
    then how can i transfer the 2nd and 3rd bits of reg1 to 3rd and 4th bits of reg2?



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    Re: VHDL Register transferring.

    by writing valid VHDL:

    reg1(2 to 3) <= reg2(3 to 4);



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    Re: VHDL Register transferring.

    Quote Originally Posted by TrickyDicky View Post
    by writing valid VHDL:

    reg1(2 to 3) <= reg2(3 to 4);
    thanks for your reply, but when i simulate the code it is showing an error
    Error (10485): VHDL error at testing.vhd(16): range direction of object slice must be same as range direction of object



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    Re: VHDL Register transferring.

    then you want downto instead.
    Please work your way through a VHDL tutorial..



    •   Alt1st August 2017, 12:25

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    Re: VHDL Register transferring.

    Quote Originally Posted by hareeshP View Post
    then how can i transfer the 2nd and 3rd bits of reg1 to 3rd and 4th bits of reg2?
    you keep asking variants of the same question that is utterly basic. please read a book or a tutorial on vhdl.
    Really, I am not Sam.



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    Re: VHDL Register transferring.

    Quote Originally Posted by ThisIsNotSam View Post
    you keep asking variants of the same question that is utterly basic. please read a book or a tutorial on vhdl.
    Besides that, switching constantly between Verilog and VHDL isn't going to help you learn either language. Pick one and learn just that one language. Once you are familiar (I don't mean you can recognize the language) with designing in that language and are comfortable with using it, then and only then, should you start studying the other language.



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    Re: VHDL Register transferring.

    Quote Originally Posted by ads-ee View Post
    Besides that, switching constantly between Verilog and VHDL isn't going to help you learn either language. Pick one and learn just that one language. Once you are familiar (I don't mean you can recognize the language) with designing in that language and are comfortable with using it, then and only then, should you start studying the other language.
    thanks for valuable advice, i am focusing on vhdl and i have a verilog source code which i need to convert it into vhdl. First of all i am understanding the logic used in the source code, that is why i am posting these kind of questions.



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    Re: VHDL Register transferring.

    You normally don't need to convert verilog into vhdl. many tools support both as long as a common subset is used at the interface between the two.

    in both languages vectors have a value and a defined way to index the bits.

    Code:
    signal a : std_logic_vector(0 to 3);
    signal b : std_logic_vector(1 to 4);
    signal c : std_logic_vector(3 downto 0);
    signal d : std_logic_vector(7 downto 4);
    
    
    a <= "X10Z"; -- a(0) = 'X', a(1) = '1'; a(2) = '0', a(3) = 'Z'; -- a(3) is the leftmost bit
    b <= a;  -- b(0) is an error.  b(1) = 'X', b(2) = '1', b(3) = '0', b(4) = 'Z';
    c <= a;  -- c(0) = 'Z', c(1) = '0', c(2) = '1', c(3) = 'X'; -- c(0) is the leftmost bit
    d <= a;  -- d(0), d(1), d(2), d(3) are not valid.  d(4) = 'Z', d(5) = '0', d(6) = '1', d(7) = 'X'
    as you can see, the value for each is the same -- "X10Z". 'X' represents "invalid" and 'Z' represents "high-impedance". These values won't be used in HW designs that often, but they are values that could be seen in simulation. They are used here to make the indexing easier to see.

    The literal "X10Z" has a default indexing scheme of "0 to 3", although this fact rarely comes up.



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