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19th July 2017, 13:28 #1
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VHDL Register transferring.
hi,
please anyone tell me
how to transfer the bits of one register to another register in vhdl?

19th July 2017, 13:28

19th July 2017, 14:10 #2
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Re: VHDL Register transferring.
Code VHDL  [expand] 1
reg2 <= reg1;

19th July 2017, 14:34 #3
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Re: VHDL Register transferring.
but i want to transfer the first bit of reg1 to first bit of reg2..

19th July 2017, 14:41 #4
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Re: VHDL Register transferring.
Code VHDL  [expand] 1
reg2(0) <= reg1(0);  assuming reg1/2 are arrays where 0th element is first bit

19th July 2017, 15:00 #5
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Re: VHDL Register transferring.
Code VHDL  [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
library ieee; use ieee.std_logic_1164.all; entity test3 is port(clk: in std_logic; ifc_a: out std_logic_vector(1 downto 0)); end test3; architecture modu of test3 is signal ifc_dout: std_logic_vector(1 downto 0); begin process(clk) then begin if(rising_edge(clk)) then ifc_a(0)<=ifc_dout(0); ifc_a(1)<=ifc_dout(1); end if; end process; end modu;

19th July 2017, 15:16 #6
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Re: VHDL Register transferring.
how to transfer the bits of one register to another register in vhdl?but i want to transfer the first bit of reg1 to first bit of reg2..
Code:ifc_a(0)<=ifc_dout(0); ifc_a(1)<=ifc_dout(1);
Code:ifc_a<=ifc_dout;

19th July 2017, 15:16

1st August 2017, 11:07 #7
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Re: VHDL Register transferring.
reg1(2:3) <= reg2(3:4);
is this valid in vhdl?

1st August 2017, 11:07

1st August 2017, 11:12 #8
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1st August 2017, 11:26 #9
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1st August 2017, 11:53 #10
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Re: VHDL Register transferring.
by writing valid VHDL:
reg1(2 to 3) <= reg2(3 to 4);

1st August 2017, 12:12 #11
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1st August 2017, 12:25 #12
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Re: VHDL Register transferring.
then you want downto instead.
Please work your way through a VHDL tutorial..

1st August 2017, 12:25

1st August 2017, 15:30 #13
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1st August 2017, 16:26 #14
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Re: VHDL Register transferring.
Besides that, switching constantly between Verilog and VHDL isn't going to help you learn either language. Pick one and learn just that one language. Once you are familiar (I don't mean you can recognize the language) with designing in that language and are comfortable with using it, then and only then, should you start studying the other language.

2nd August 2017, 05:15 #15
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2nd August 2017, 06:15 #16
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Re: VHDL Register transferring.
You normally don't need to convert verilog into vhdl. many tools support both as long as a common subset is used at the interface between the two.
in both languages vectors have a value and a defined way to index the bits.
Code:signal a : std_logic_vector(0 to 3); signal b : std_logic_vector(1 to 4); signal c : std_logic_vector(3 downto 0); signal d : std_logic_vector(7 downto 4); a <= "X10Z";  a(0) = 'X', a(1) = '1'; a(2) = '0', a(3) = 'Z';  a(3) is the leftmost bit b <= a;  b(0) is an error. b(1) = 'X', b(2) = '1', b(3) = '0', b(4) = 'Z'; c <= a;  c(0) = 'Z', c(1) = '0', c(2) = '1', c(3) = 'X';  c(0) is the leftmost bit d <= a;  d(0), d(1), d(2), d(3) are not valid. d(4) = 'Z', d(5) = '0', d(6) = '1', d(7) = 'X'
The literal "X10Z" has a default indexing scheme of "0 to 3", although this fact rarely comes up.
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