usuikazkou
Junior Member level 2
Hi guys, recently I tried to design a CML latch, do an AC analysis of CML latch is necessary? 1. No matter with or without inductor peaking, how to run the AC analysis?
2. Could common mode and swing of the data input and clock input the same?
Thank you.
I have read a lot of material, but I still don't know how to decide the variable and doing the simulation, I am using 45nm with 0.9 VDD.
2. Could common mode and swing of the data input and clock input the same?
Thank you.
I have read a lot of material, but I still don't know how to decide the variable and doing the simulation, I am using 45nm with 0.9 VDD.