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asynchronus to synchronous

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Johannah

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Hi,

The picture I have attached is an asynchronous code. However, my library does not contain asynchronous reset. How do I modify my code into synchronous preserving it's functionality. Please help I'm newbie in RTL coding

Thanks
 

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The attached is not a very good description of a system having clock and async reset.

In order to convert do this:
You can have a MINIMUM of two consecutive flip flops, with the async-reset input connected to both of their reset pins and the clock to both of their clock pins.
The output from the second flip flop (Q pin) will be a synchronous reset.
 

dpaul said:
In order to convert do this:
You can have a MINIMUM of two consecutive flip flops, with the async-reset input connected to both of their reset pins and the clock to both of their clock pins.
The output from the second flip flop (Q pin) will be a synchronous reset.
Click to expand...
??? Not sure what question you are trying to answer. The OP was asking how to convert a Async reset code into a Sync reset code.

Johannah said:
Hi,

The picture I have attached is an asynchronous code. However, my library does not contain asynchronous reset. How do I modify my code into synchronous preserving it's functionality. Please help I'm newbie in RTL coding

Thanks
Click to expand...
Next time insert the code directly in you post with tags, don't use a picture.

your async reset code:
Code Verilog - [expand]
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always @(posedge mclk or posedge puc_rst)
  if (puc_rst)              pmem_dout_bckup_sel <=  1'b0;
  else if (fe_pmem_save)    pmem_dout_bckup_sel <=  1'b1;
  else if (fe_pmem_restore) pmem_dout_bckup_sel <=  1'b0;
 
assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout;


equivalent sync reset code:
Code Verilog - [expand]
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always @(posedge mclk)
  if (puc_rst)              pmem_dout_bckup_sel <=  1'b0;
  else if (fe_pmem_save)    pmem_dout_bckup_sel <=  1'b1;
  else if (fe_pmem_restore) pmem_dout_bckup_sel <=  1'b0;
 
assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout;

Note: if the clock mclk is not running (or stops running) the register output pmem_dout_bckup_sel will hold the last value it had.
 

dpaul said:
The attached is not a very good description of a system having clock and async reset.

In order to convert do this:
You can have a MINIMUM of two consecutive flip flops, with the async-reset input connected to both of their reset pins and the clock to both of their clock pins.
The output from the second flip flop (Q pin) will be a synchronous reset.
Click to expand...

you are describing a synchronizer. it's useful when you have to go through different clock domains, but it is not what the OP is asking.
 

my library does not contain asynchronous reset
Click to expand...
I'm wondering about the reasonability of this statement. All ASIC libraries that I know have DFF cells with and without asynchronous inputs. But ASIC isn't my business, you may correct me in this regard.

As ads-ee explained, changing the reset into synchronous can't exactly preserve the functionality. You need to verify the function for your reset conditions.

Generally, changing the reset to synchronous shifts the effort to combinational logic in front of DFFs. As some reset terms can be probably combined with existing logic during synthesis, the overall effort may be reduced.
 

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