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    question about use two CMT in different primitives in spartan 6

    hi every one,
    I have a spartan 6(XC6SLX150) which it's input clock is a differential pair and it's value is 12.8Mhz, I understood which I couldn't use pll_base because it's minimum input frequency should be 19MHz. If I want to use Pll_base can I produce a frequency higher than 12.8 MHz with CMD_CLKGEN and define it's output clock to a signal in top module and define this signal as the input of another cmt and use this as the input of the base_pll? I mean it doesn't matter that the input of the pll_base does not enter from gclk and it's a signal which this signal is the output of the DCM_CLKGEN?please if it is not a correct path tell me the correct path :)
    Regards
    Matin

    •   Alt17th July 2017, 09:04

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  2. #2
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    Re: question about use two CMT in different primitives in spartan 6

    Quote Originally Posted by matin-kh View Post
    hi every one,
    I have a spartan 6(XC6SLX150) which it's input clock is a differential pair and it's value is 12.8Mhz, I understood which I couldn't use pll_base because it's minimum input frequency should be 19MHz. If I want to use Pll_base can I produce a frequency higher than 12.8 MHz with CMD_CLKGEN and define it's output clock to a signal in top module and define this signal as the input of another cmt and use this as the input of the base_pll? I mean it doesn't matter that the input of the pll_base does not enter from gclk and it's a signal which this signal is the output of the DCM_CLKGEN?please if it is not a correct path tell me the correct path :)
    Regards
    Matin
    you should read ug382, it shows on pg 88, the following two figures.
    Click image for larger version. 

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    The top one seems to answer you question about connecting the DCM_CLKGEN to a PLL_BASE, which appears to be a direct connection with no buffers required. The bottom one seems to indicate you can generate a "clock" which is free running based off the input of 12.8 MHz, but will drift in frequency over PVT, though the datasheet seems to indicate the CLKIN input must be 20 MHz minimum, though that is defined for the spread spectrum mode and not the free running mode.

    Why don't you just use a DCM_SP and use the 2x output that will make the 12.8 MHz into a 25.6 MHz clock and that frequency can be input into the PLL CLKIN pin.


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    •   Alt17th July 2017, 17:26

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    Re: question about use two CMT in different primitives in spartan 6

    thank you very much in advance for your reply. it makes no difference for me to use DCM_CLKGEN or DCP_SP if I use DCM_SP it is ok to define it's output as a signal and then run another clocking wizard and use this signal as the input of the DCM_SP?
    like this:
    Code VHDL - [expand]
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    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
     
    entity test is
        Port ( clk_p : in  STD_LOGIC;
                  clk_n : in  STD_LOGIC;
                  clk1 :out std_logic;
                  clk2 :out std_logic;
                  clk3 :out std_logic;
                  clk4 :out std_logic;
                  clk5 :out std_logic;
                  clk6 :out std_logic);
    end test;
     
    architecture Behavioral of test is
     
    component ip1
    port
     (-- Clock in ports
      CLK_IN1_P         : in     std_logic;
      CLK_IN1_N         : in     std_logic;
      -- Clock out ports
      CLK_OUT1          : out    std_logic
     );
    end component;
     
    component ip2
    port
     (-- Clock in ports
      CLK_IN1           : in     std_logic;
      -- Clock out ports
      CLK_OUT1          : out    std_logic;
      CLK_OUT2          : out    std_logic;
      CLK_OUT3          : out    std_logic;
      CLK_OUT4          : out    std_logic;
      CLK_OUT5          : out    std_logic;
      CLK_OUT6          : out    std_logic
     );
    end component;
    signal x:std_logic;
    begin
     
    u1 : ip1 port map(-- Clock in ports
        CLK_IN1_P => clk_p,
        CLK_IN1_N => clk_n,
        -- Clock out ports
        CLK_OUT1 => x);
     
    u2 : ip2
      port map
       (-- Clock in ports
        CLK_IN1 => x,
        -- Clock out ports
        CLK_OUT1 => CLK1,
        CLK_OUT2 => CLK2,
        CLK_OUT3 => CLK3,
        CLK_OUT4 => CLK4,
        CLK_OUT5 => CLK5,
        CLK_OUT6 => CLK6);
         
    end Behavioral;

    at the above IP1 is the first CMT which i used DCM_BASE and IP2 is the second CMT which i used PLL_BASE.



    •   Alt18th July 2017, 05:39

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  4. #4
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    Re: question about use two CMT in different primitives in spartan 6

    Did you at least try and see if the clocking wizard would allow you to cascaded the DCM_BASE with a PLL_BASE without resorting to two different CMTs? I thought it would allowed that configuration.

    If it doesn't then you'll need a clock buffer between the DCM_BASE and the PLL_BASE as their will be no direct route between the two CMTs.

    BTW, you should start now (early in your career, to make it a habit) making signal names and ip names more descriptive than things like ip1, ip2, x, etc (which are utterly meaningless names and give zero clue as to what they are for).


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