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About this voltage controlled current source

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sys_eng

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On the diagram, circuit on the right
1)how does Vi comes across into Ri?It's not obvious to me. iO is Vi / Ri. I see vFB across Ri but I don't see Vi across Ri.
 

The circuit acts like a differential input operational amplifier and, with the negative feedback from the resistor to the negative input, strives to keep the voltage at its negative input equal to its positive input.
Any deviation of the minus input from the positive input will cause the output to change until the two voltages are again equal.
This means the voltage across R1 equals Vi.

Make sense?

If it's still not clear, try reading some tutorials on operational amplifiers.
 
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The circuit acts like a differential input operational amplifier and, with the negative feedback from the resistor to the negative input, strives to keep the voltage at its negative input equal to its positive input.
Any deviation of the minus input from the positive input will cause the output to change until the two voltages are again equal.
This means the voltage across R1 equals Vi.

Make sense?

If it's still not clear, try reading some tutorials on operational amplifiers.

Couple things.
1)the IBias on MT and M5 are not the same right?
2)if IBias on M5 increase VG would decrease and vice versa.
 
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    FvM

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For lowest amplifier offset voltage, MT would have double the area of M5 and double the bias current.
 

1)the IBias on MT and M5 are not the same right?
2)if IBias on M5 increase VG would decrease and vice versa.
1) If MT and M5 are the same size transistors then their ideal bias currents will be the same.

2) No, VG would increase with an increase in IBias.
 

1) If MT and M5 are the same size transistors then their ideal bias currents will be the same.

2) No, VG would increase with an increase in IBias.

On number 2, increased IBias M5 , same as increased at M4 would cause greater pull up or pulldown? Greater pullup means VG increased. And greater pull down VG will decrease.

On case if VI < VFB, most IBias at MT would flow through M1 instead of M2 which means IBias at M5 will increase.

Case of VI >VG, most IBias at MT flow through M2 and IBias at M5 will decrease.
 

current_source.png
I can't simulate the above circuit. I expect VFB to be 2VDC , tracking VI but I got 0V. what's wrong?
 

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Try removing M5's drain from ground and connect it to M4's drain.

Why? Looking original circuit. M2 which is M5 in simulated circuit has the drain connected to ground. M2, M1 sources connected together that's why I have M4, M5 sources connected together.
 

With floating Vout node, you'll hardly achieve any current through R1 or non-zero Vfb.

Even with M9 drain tied to Vdd, the circuit dimensioning is most likely unsuitable for M9 Id of 2 mA.
 

With floating Vout node, you'll hardly achieve any current through R1 or non-zero Vfb.

Even with M9 drain tied to Vdd, the circuit dimensioning is most likely unsuitable for M9 Id of 2 mA.

My vout is not floating, I added an inverter to Vout
 

Hi,

Where's the load then?

It's not much help, but when simulating a few simple and simple-ish op amps, I found that VBias is not best discovered by guesswork - I had loads of problems in all sorts of beginner's op amps in the simulations where VBias had to be calculated or guessed; I didn't find that setting it at, e.g. 0V for PMOS/PNP was especially effective, and seeing results to me it seemed more to the point incorrect as a bias point. I'm just a hobbyist so what would I know.

Maybe check the book and see if it gives an explanation of what VBias should actually be.
 
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    FvM

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You're ignoring the simple fact that M9 needs a positive Vds for operation. There must be a load able to maintain the voltage under current. Connecting another high impedance node (the inverter input) can't solve the problem.
 

You're ignoring the simple fact that M9 needs a positive Vds for operation. There must be a load able to maintain the voltage under current. Connecting another high impedance node (the inverter input) can't solve the problem.

OK, I added a pullup resistor to the M9 and treat it as open drain output(M9's drain).

still VFB doesn't track VI, VI=2V and VFB only 665.2mV
amp_simul13.png
 

Vgs(M4)=2-0.6026=1.3974V , Vgs(M5)=0.6652V and Ids(M5)>Ids(M4)..
How it's possible ??
 

still VFB doesn't track VI, VI=2V and VFB only 665.2mV
You obviously realized that M9 isn't able of sourcing 2 mA, thus you changed R1 to 10k. Unfortunately M9 can't even source 200 µA.

Next step towards real CMOS design is to size transistors appropriately, e.g. give M9 a width multiplier of 16 or more.
 

Vgs(M4)=2-0.6026=1.3974V , Vgs(M5)=0.6652V and Ids(M5)>Ids(M4)..
How it's possible ??
typo,

VI=2, VG=3.24, IBias(M2)=3.63uA VFB=665.2mV
VI=0, VG=2.876, IBias(M2)=26.17uA VFB=544mV

- - - Updated - - -

You obviously realized that M9 isn't able of sourcing 2 mA, thus you changed R1 to 10k. Unfortunately M9 can't even source 200 µA.

Next step towards real CMOS design is to size transistors appropriately, e.g. give M9 a width multiplier of 16 or more.


what's default W if I don't specified it? If I put W=1u the current drops to 1.071uA. So the unspecified or default W is not 1u.

- - - Updated - - -

You obviously realized that M9 isn't able of sourcing 2 mA, thus you changed R1 to 10k. Unfortunately M9 can't even source 200 µA.

Next step towards real CMOS design is to size transistors appropriately, e.g. give M9 a width multiplier of 16 or more.

No, man I have change M9 W=1500u in order to have VFB=VI=2V. not 16 multiplier. 1500u is too big to be realized on chip.
amp_simul14.png
 

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