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  1. #1
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    VHDL array comparison

    I have a command buffer from an input of a UART and I want to decode various commands to perform actions in a FSM. I have created an array of 80 characters and in this example I want to see if the word Print has been entered, however, this does not compile.


    type InputBufferType is array (0 to 80) of std_logic_vector(7 downto 0);
    signal CommandBuffer : InputBufferType;

    if commandBuffer(0 to 4) = "Print" then

    Any suggestions are welcome !

    •   Alt16th July 2017, 12:35

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  2. #2
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    Re: VHDL array comparison

    Thats because "Print" is an array of characters.
    Your input buffer is an array of std_logic_vector.

    You will have to compare each entry to indvidual ascii codes

    I will note though, this is a very inefficient design and likely to have a slow clock speed, as you are comparing many different length commands and building some large logic trees. Had you considered the design before you wrote the code? would a ram have been better than this array of registers?
    Could you not process the words on every clock cycle with a state machine, rather than buffering them all and having to do a large parrallel compare?



    •   Alt16th July 2017, 15:01

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  3. #3
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    Re: VHDL array comparison

    Thanks for this, I rearranged to

    if commandBuffer(0)= x"50" and
    commandBuffer(1)= x"72" and
    commandBuffer(2)= x"69" and
    commandBuffer(3)= x"6E" and
    commandBuffer(4)= x"74" then
    cmd <= Print;

    Answer to your points, as this is a temporary solution for a proof of concept, I was looking for a quick / simple method. I did consider using RAM but thought the registers would be simpler to use.
    However, I am intrigued about the issue with large parallel compare, if I did this character at a time, I would still have the same number of comparison right ? or am I (most likely) missing the point ? Also, I can not see how I could do a compare serially to workout what the command would be (there are only 6-7 commands), so if you could point me in the right direction, I would certainly give it a go.

    Thanks again.



    •   Alt17th July 2017, 09:10

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  4. #4
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    Re: VHDL array comparison

    Currently this requires N comparators, with the results all anded together, with many idle cycles as the letters are read in.
    Doing the compare each clock cycle only requires 1 comparator, as you are just looking for individual letters, This gives many fewer idle cycles. The state machine would control which letter you were currently looking for.



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