sherline123
Member level 2
Hi~
I was reading some materials and confusing about logical efforts. I did make a search at here but seem none of them can clear my doubts.
From my understandings, logical effort is measuring ability to deliver current when compared to an inverter.
That's why we get G for inverter =1; while NAND=4:3; NOR=4:3
When it goes to Skew gates, it seem to be more complicated. We got rising and falling logical efforts. So we need to compare to an unskewed version of inverter which rising and falling. An unskew rising inverter is 2:1 ratio of P to Nmos while falling will be 1:0.5. So did this mean we need to convert a given logic gate into a rising version and a falling version if we want to calulate its logical effort?
Things are getting more complicated when it go to Pseudo-nmos. I don't understand how to calculate the logical effort of rising and falling for Pseudo-nmos at all. Kindly explain and clear my doubts.
I was reading some materials and confusing about logical efforts. I did make a search at here but seem none of them can clear my doubts.
From my understandings, logical effort is measuring ability to deliver current when compared to an inverter.
That's why we get G for inverter =1; while NAND=4:3; NOR=4:3
When it goes to Skew gates, it seem to be more complicated. We got rising and falling logical efforts. So we need to compare to an unskewed version of inverter which rising and falling. An unskew rising inverter is 2:1 ratio of P to Nmos while falling will be 1:0.5. So did this mean we need to convert a given logic gate into a rising version and a falling version if we want to calulate its logical effort?
Things are getting more complicated when it go to Pseudo-nmos. I don't understand how to calculate the logical effort of rising and falling for Pseudo-nmos at all. Kindly explain and clear my doubts.
