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why does PMOS and NMOS tying its ground to its source?

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sys_eng

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PSpice NMOS model with body tied to source

nmos.png

usually body should tied to ground for nmos.

why is it tied to the source? The source and body shouldnt be the same, right?
 

Re: PSpice NMOS model with body tied to source

The connection is mandatory by design for vertical MOSFET (all power MOSFET), and also usual for discrete small signal MOSFET (amplifiers, switches). A few discrete types with separate substrate terminal are available.
 

Re: PSpice NMOS model with body tied to source

The connection is mandatory by design for vertical MOSFET (all power MOSFET), and also usual for discrete small signal MOSFET (amplifiers, switches). A few discrete types with separate substrate terminal are available.

Shouldn't be like that.cascode.png

if M2 body tied to its source which is connected to drain of M1, then its wrong.

M2 body should tied to ground and shouldn't tie to its source.
 

Re: PSpice NMOS model with body tied to source

Shouldn't be like that.
What are you talking about? PSPICE symbols? MOSFETs on the market?

I don't exactly understand what your question is.

If you want to model MOSFETs with separate substrate, e.g. for IC design, you can do this in PSPICE. The MOSFET model has separate substrate and source terminals in any case. You preferred to use the MBreakN PSPICE symbol, which is appropriate for many technical MOSFET. If you want to model MOSFET with separate substrate, use MBreakN4.
 

Re: PSpice NMOS model with body tied to source

What are you talking about? PSPICE symbols? MOSFETs on the market?

I don't exactly understand what your question is.

If you want to model MOSFETs with separate substrate, e.g. for IC design, you can do this in PSPICE. The MOSFET model has separate substrate and source terminals in any case. You preferred to use the MBreakN PSPICE symbol, which is appropriate for many technical MOSFET. If you want to model MOSFET with separate substrate, use MBreakN4.

I am just saying I cannot use MBreakN Pspice for the 2nd picture then?
 

Re: PSpice NMOS model with body tied to source

No, use MBreakN4.
 
I have seen pspice schematic transistor symbol have all its body tying to it source.
what's the reason for that?
 

Body potential deviating from source too far can wake
up the parasitic bipolar within (forward bias = base current).

Reverse biasing body slightly can reduce leakage but then
you need an "outside the rails" potential.

Discrete power MOSFETs do this internally so you only
see a 3-termninal device; then the simulator schematic
is only doing its best to represent the piece-part reality.
 
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    CataM

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I have seen pspice schematic transistor symbol have all its body tying to it source.
what's the reason for that?
Because most MOSFETS have the body internally tied to the one of channel connections which then makes it the source.
Otherwise the source and drain are interchangeable.
 

Most power MOSFETs (discrete VDMOS, integrated
LDMOS) are designed fundamentally asymmetric and
only the "regular" integrated MOSFET is commonly
symmetric (interchangeable S/D). Still the body is
fundamental to the voltage blocking and has to be
"pinned" (stiff voltage source) to ensure the D-B
blocking junction leakage does not end up going
into B-S junction (=B-E) forward biasing.
 
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    CataM

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Most power MOSFETs (discrete VDMOS, integrated
LDMOS) are designed fundamentally asymmetric and
only the "regular" integrated MOSFET is commonly
symmetric (interchangeable S/D). Still the body is
fundamental to the voltage blocking and has to be
"pinned" (stiff voltage source) to ensure the D-B
blocking junction leakage does not end up going
into B-S junction (=B-E) forward biasing.
Ok, let's talk about the regular MOS. Interchangeable? Is that mean the body is tied to it's drain?
 

Refer the cross section view of MOSFET below,



The source and the drain terminal are 'n+ doped region' and the body is p-type substrate. Between "S" and "Body" (also "D" and Body) a diode is present, which must not be forward biased. Hence, the voltage at the "Body" terminal must not be higher than the smaller voltage of either "S" or "D" terminal.

To achieve the above mentioned condition, the "Body" terminal is either connected to lowest voltage available (usually GND/0V) or the terminal of the transistor with the lower voltage. By definition the "S" terminal is having the lower voltage. Hence, the "Body" terminal is connected to "S" terminal.

Generally, the manufacturer connects the "Body" terminal to the "S" terminal so that one of the diodes can never be forward biased and this leaves the other diode able to be forward biased.
 
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    CataM

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Interchangeable means, as shown in the cross section,
that there is no structural difference between "S" and
"D" implant regions - they are assigned a connectivity,
but are physically identical. You could tie the B terminal
to either one, or to another potential that ensures that
the junctions are all reverse biased (or, you could play
body-biasing games looking for less leakage, more drive,
or even actively commutate the body (ala "dynamic
threshold", B=G, configurations).

If you tie B to D and D is biased as normal (NMOS, D
has a higher voltage than S) then you have "broken"
some of the standard MOSFET assumptions (like all
junctions reverse biased), and possibly wake up the
lateral NPN that sits below the channel. But if you simply
decide that the "Drain" is going to be biased at 0 and the
"Source" is going to swing 0 - 2.5V, and tie body to
"Drain", that is plain normal with only a connectivity
mis-naming (discrepancy, name vs functionality).

VDMOS and LDMOS have asymmetric structures by
design and swapping names also swaps functionality
(if indeed such swappage is even possible - hard
layout connections B=S are the norm for power
devices).
 

Most power MOSFETs (discrete VDMOS, integrated
LDMOS) are designed fundamentally asymmetric and
only the "regular" integrated MOSFET is commonly
symmetric (interchangeable S/D). Still the body is
fundamental to the voltage blocking and has to be
"pinned" (stiff voltage source) to ensure the D-B
blocking junction leakage does not end up going
into B-S junction (=B-E) forward biasing.

Refer the cross section view of MOSFET below,



The source and the drain terminal are 'n+ doped region' and the body is p-type substrate. Between "S" and "Body" (also "D" and Body) a diode is present, which must not be forward biased. Hence, the voltage at the "Body" terminal must not be higher than the smaller voltage of either "S" or "D" terminal.

To achieve the above mentioned condition, the "Body" terminal is either connected to lowest voltage available (usually GND/0V) or the terminal of the transistor with the lower voltage. By definition the "S" terminal is having the lower voltage. Hence, the "Body" terminal is connected to "S" terminal.

Generally, the manufacturer connects the "Body" terminal to the "S" terminal so that one of the diodes can never be forward biased and this leaves the other diode able to be forward biased.

Well, I find circuit of nmos with it's body tied to ground versus body tied to source have different voltage output.

So, which one we should use??
 

The behaviour of MOSFET is due to body effect (back-gate effect).

The threshold voltage (Vth) of MOSFET is related
to Vsb (source-bulk voltage).

The body effect refers to the changes in the threshold voltage by the change in Vsb. Because the body influences the threshold voltage (when it is not tied to the
source), it can be thought of as a second gate (back gate). Consider the following cases,

Case 1 :
If the substrate is at 0V/GND, then you will not see body effect but if the substrate voltage is lower than 0V then the electrons will need more positive gate potential to get attracted towards the channel because the substrate potential is acting against the gate potential thus you will see the Vth of the NMOS getting increased. This is body effect. Note: It assumes source is at ground.

Case 2:
Body effect will happen, if VB is at ground and the voltage of source is increased.

Another thing, if your MOSFET is in linear operation, when the source is
connected to bulk, you don't have to deal with the "transconductance" due to Vbs (gmb), since Vbs = 0.
 

The behaviour of MOSFET is due to body effect (back-gate effect).

The threshold voltage (Vth) of MOSFET is related
to Vsb (source-bulk voltage).

The body effect refers to the changes in the threshold voltage by the change in Vsb. Because the body influences the threshold voltage (when it is not tied to the
source), it can be thought of as a second gate (back gate). Consider the following cases,

Case 1 :
If the substrate is at 0V/GND, then you will not see body effect but if the substrate voltage is lower than 0V then the electrons will need more positive gate potential to get attracted towards the channel because the substrate potential is acting against the gate potential thus you will see the Vth of the NMOS getting increased. This is body effect. Note: It assumes source is at ground.

Case 2:
Body effect will happen, if VB is at ground and the voltage of source is increased.

Another thing, if your MOSFET is in linear operation, when the source is
connected to bulk, you don't have to deal with the "transconductance" due to Vbs (gmb), since Vbs = 0.


so I can use option2 all the time because its more convenient? Pls note, the following 2 options generate different voltage outputs at the drain
option.png
 

The background of your question isn't quite clear. If you are asking about analog IC design, the substrate connection options are imposed by the technology, you are not free to choose it at will.
 

so I can use option2 all the time because its more convenient? Pls note, the following 2 options generate different voltage outputs at the drain
View attachment 139954
If you want to operate the MOSFET in linear operation, then it is better to connect the source to body (if there is separate terminal for body).
Nowadays, the MOSFET are doesn't have separate body terminal ( internally connected to source during IC fabrication), then you don't have the choice.
 

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