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D-Flipflop: On power up, what is the default STATE of pin Q

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jeevaaraam

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I have used following part in one of my design.

Part #: 74HCT74PW
Function: D-type ?ip-?op
Description: Dual D-type ?ip-?op with set and reset; positive-edge trigger;

TTL-enabled

Refer attached circuit diagram.

The Net ‘CNT_RST’ is connected to GPO of microcontroller to clear the flip-flop.

The Net ‘RESET_CNT’ is connected to GPI of microcontroller to get the status.

Clarification required:
My expected output will be HIGH, only when the SD=HIGH, RD=HIGH and also CP is in

positive rising edge. But, I’m getting output pin-5 (1Q) as HIGH, when the CP is

in low state (While power ON). Whether my understanding is correct or not.


On power up, what is the STATE of pin Q (When CP = 0)?
 

Short answer: Indeterminate.

You should assert your reset signal after power-up if you want to be sure that the Q output is low.
 

Short answer: Indeterminate.

You should assert your reset signal after power-up if you want to be sure that the Q output is low.

I had added pull down resistor (1k) at the output pin Q (pin 5) to define the state of the pin. I have observed that the output is always LOW (0V), even the CP is in positive rising edge. The output should go to logic HIGH, when CP is in positive rising edge.
 

I had added pull down resistor (1k) at the output pin Q (pin 5) to define the state of the pin.
Just useless.

Consider that by circuit design RESET_CNT swings between Vcc/2 and Vcc and thus never sends a valid low logic level.
 

I had added pull down resistor (1k) at the output pin Q (pin 5) to define the state of the pin. I have observed that the output is always LOW (0V), even the CP is in positive rising edge. The output should go to logic HIGH, when CP is in positive rising edge.

You can't force the state of the output with a pull down or pull-up. if the FF is driving Q high all your "pull down" is doing is drawing current.
 

The state change is defined in the manufacturer datasheet as follows,



From this, the output will be HIGH, only when CP is in rising edge. Then, the output may not be in indeterminate state.

--

Refer attached waveform Vcc (vs) CP (vs) D (vs) 1Q




When the Vcc is ON,
o Clock (CP) is in LOW state,
o Data input-1 is going HIGH and
o Output (1Q) is going to HIGH.

Note: Pin 1R#D and 1S#D were pulled-up.

From this, the voltage levels are 0V for LOW logic and 4.9V for HIGH logic (ie., sufficient to set the logic).


I have used this flip-flop to latch a error bit (in HIGH state), only when the CP (will be generated based on the error condition) is in rising edge. Since, the 1Q is in HIGH state on power up, I'm getting false error bit (as per my application), irrespective of CP.

Was the 1Q (Output) is defined based on 1D (Data In - pulled-up) on power up?
 

That is a naive reading of the data sheet. It says nothing of the power-up state. You have actually SEEN that the Q output does not come up as you expected, yet you persist in ignoring the fact that you need to assert a reset to get the ff into a known state.
 

That is a naive reading of the data sheet. It says nothing of the power-up state.

Yes, You are correct, the default state is not mentioned in the datasheet. The default state had got from manufacturer support team before designing. The simulation results show as LOW state (Again, It is also based on the model, may not give the actual IC characteristics)
 

Yes, You are correct, the default state is not mentioned in the datasheet. The default state had got from manufacturer support team before designing. The simulation results show as LOW state (Again, It is also based on the model, may not give the actual IC characteristics)

Well, I don't believe the support team. They don't know what your power-on ramp looks like. You might try putting a small (100pF) cap on the reset input to hold it low a bit longer on power up so it will force a reset.
 

just reset the damn thing. no one would trust a flop to behave in a deterministic way on power up.
 

With reference to the default state of the D flip flop output is HIGH (As per physical measurement on CCA-2Nos and assuming that is constant), I have done the following implementation to resolve the issue (actually trying to resolve!)

I have changed the expected output as LOW, when event is occurred (CP is in rising edge). Then, the state change will happen from HIGH (Default on POWER ON) to LOW.

1. The data input (U4/2) is pulled down to GND state.
2. 1R#D reset pin (U4/1) is removed from GPO (CNT_RST) and there is no change in pull-up.
3. 1S#D set pin (U4/4) is connected to GPO (CNT_RST) along with pull-up for resetting the flip-flop whenever required.
4. Hence, when the clock pulse CP is in positive rising edge, the output will be in LOW state.

Modified circuit :

My logic is working fine (As on now!). But, I'm sure that this will not be permanent solution.

If the default state of the D flip flop output is indeterminate state, I cannot expect "HIGH" for all the CCAs (to be made).

Will it be the solution for this issue?

- - - Updated - - -

You might try putting a small (100pF) cap on the reset input to hold it low a bit longer on power up so it will force a reset.

As other option, I want to include power ON pulse (Active LOW) generator (For Eg: LTC6995). The output will be connected to 1S#D pin. While power ON, the IC
will generate Active LOW pulse and it will set the output of flipflop to HIGH state (As defined in the datasheet). I hope that single pulse is sufficient to make the flipflop output to a defined state (HIGH in this case).

- - - Updated - - -

As other option,

It may happen in the next version of the PCB. It is not possible to implement in the current CCA.
 

I have changed the expected output as LOW, when event is occurred (CP is in rising edge). Then, the state change will happen from HIGH (Default on POWER ON) to LOW.

Changing the polarity of the logic does not solve your problem. It's a bad idea. A very bad idea. Just because one flipflop powered up with Q high doesn't mean they all will. If this design is going into a product, you better be prepared for a lot of angry customers.

Your second option solves nothing. You can put all the pulses you want on the D input and it's not going to change anything. You could put the pulse on the SET or RESET input.

You need to understand two things:
1) The flip flop will power up in an indeterminate state.
2) If you don't actively set it or reset it, you WILL NEVER KNOW what state it is in.
 
12 replies and you still insist on using a misguided approach to fixing the problem. I predict a short engineering career.

If you don't actively reset the FF after power up you better be prepared to have all fingers pointing at you when the field returns start arriving for an entire lot of devices, because that particular lot of FFs all power up differently than another lot.

You are using a microcontroller to interface with the FF, and you have the reset connected to the GPIO, reset it as the very first command after your bootloader runs and your main program starts. This is typically referred to as initialization of the board. Why is this so !@#$%^ hard to do!?
 
Last edited:

As I mentioned earlier, this flipflop is used to latch error bit, which is actually generated based on the number of uC reset (done by WDM, not power ON reset ) for particular time. There is a hardware circuit (which is working fine) to make this bit and this has given as cp of mentioned flipflop. Once the uC is booted, the flipflop output will give the error status to uC (you have been resetted n times within x seconds)

If this is the case, I can't simply reset the flipflop through GPO, when the uC is booting. If I'm resetting during boot-up, there is no meaning of implementing this circuit. I hope that this is not a that much simple circuit to implement and I'm not simply playing (as in hobby project) with only a uC and flipflop.

- - - Updated - - -

Your second option solves nothing. You can put all the pulses you want on the D input and it's not going to change anything. You could put the pulse on the SET or RESET input.

You need to understand two things:
1) The flip flop will power up in an indeterminate state.
2) If you don't actively set it or reset it, you WILL NEVER KNOW what state it is in.

Yes, I understood.

(Refer my second approach) That why I want set the pin 1S#D, while power ON using POR pulse generator. Then, the flipflop output will be in defined state.
 

So you circuit is used to count the number of WDT resets, then use the 100 pF cap suggested in #9. So the FF gets a proper PoR. Probably want to change R61 in your first post to something bigger like 10K.

Appears PoR wasn't considered when the design was done. I'd say the LTC6995 is overkill, TI makes the LP3470 that is cheaper. Of course if you really need a reset that can last 4.8 hours then by all means get the LTC6995.
 

You could also do this with software. If you are using something like a PIC, the watchdog timer sets a flag after the timer expires. This flag will remain set until you clear it. Thus, you can have your code periodically look at watchdog-timer-expired bit and see if an event has occurred. You can increment some counter (which doesn't get clobbered by reset). This all depends on your actual hardware, but hopefully you get the idea.
 

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