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Design Compiler (Vision)

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amol_elec

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Hello all,

How can i synthesis a design using my specified cells? In other words, I want the compiler to use only the cells that i specified (from a list or something) to synthesis the design.
 

Hello all,

How can i synthesis a design using my specified cells? In other words, I want the compiler to use only the cells that i specified (from a list or something) to synthesis the design.

there is a command for that: set_dont_use
 

there is a command for that: set_dont_use

Thank you but I Know that, but it's a very time consuming work and i'm seeking a better way to do that. In other words I just want to exactly say "WHAT" cells to be used not what cells not to be used.

Regards
 

Thank you but I Know that, but it's a very time consuming work and i'm seeking a better way to do that. In other words I just want to exactly say "WHAT" cells to be used not what cells not to be used.

Regards

this is ridiculous. it takes two lines to do what you want with the command I pointed out.

the time that it took you to reply to this post could have been used to read the documentation of the command I pointed out. you would save me some time, save you some time, and would even look less foolish.
 
There are several cells in the library, so applying the command to many cells one by one is very inefficient. By the way it seems that there is no reasonable answer to this question by now. However thank you for your time to replying me.
 

There are several cells in the library, so applying the command to many cells one by one is very inefficient. By the way it seems that there is no reasonable answer to this question by now. However thank you for your time to replying me.

Go read the documentation. What you want can be achieved with 2 lines of code. Like I told you before. Hint: wildcards.
 

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