+ Post New Thread
Results 1 to 6 of 6
  1. #1
    Junior Member level 1
    Points: 554, Level: 5

    Join Date
    Jan 2015
    Posts
    15
    Helped
    0 / 0
    Points
    554
    Level
    5

    Difference b/w asynchronous Vs synchronous FIFO

    Can you tell me, what is the main difference between synchronous and asynchronous fifo as per the design!! Does usage of gray counter alone in design makes all the sense for asynchronous design? I am having this doubt can anyone clarify...

    •   Alt7th July 2017, 12:53

      advertising

        
       

  2. #2
    Advanced Member level 5
    Points: 34,876, Level: 45
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,391
    Helped
    1862 / 1862
    Points
    34,876
    Level
    45

    Re: Difference b/w asynchronous Vs synchronous FIFO

    A synchronous fifo would use the same clocks for read and write
    asynchronous uses different clocks.

    Grey coding of the address can be a good idea in asynchronous fifos as it minimises problems crossing the clock domains - but it can be done safely without grey coding.


    1 members found this post helpful.

    •   Alt7th July 2017, 13:37

      advertising

        
       

  3. #3
    Junior Member level 1
    Points: 554, Level: 5

    Join Date
    Jan 2015
    Posts
    15
    Helped
    0 / 0
    Points
    554
    Level
    5

    Re: Difference b/w asynchronous Vs synchronous FIFO

    Thank you for the info.
    Actually i had generated my read address and write address then
    i am using the conditions of MSB's to check whether it is empty or full for synchronous fifo. When i wanted to use the same logic for asynchronous fifo adding delays for write address and read address will be sufficient without going for grey coding?? Can you suggest..



    •   Alt10th July 2017, 06:28

      advertising

        
       

  4. #4
    Advanced Member level 5
    Points: 34,876, Level: 45
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,391
    Helped
    1862 / 1862
    Points
    34,876
    Level
    45

    Re: Difference b/w asynchronous Vs synchronous FIFO

    1. Why are you building a FIFO at all? Altera and Xilinx provide FIFO ip for free already.
    2. Why are you only checking the MSBs? you need to check the whole address. What happens when only 1 element is written to the FIFO?
    3. You might get away with it - but grey coding will minimise the bit transition and hence any possible errors.


    1 members found this post helpful.

  5. #5
    Junior Member level 1
    Points: 554, Level: 5

    Join Date
    Jan 2015
    Posts
    15
    Helped
    0 / 0
    Points
    554
    Level
    5

    Re: Difference b/w asynchronous Vs synchronous FIFO

    yes i am building it in simulink,
    Even i am checking the whole address like the conditions are (read_addr[8:0] == write_addr[8:0]) empty is enabled.
    and ((read_addr[7:0]==write_addr[7:0])&&(read_addr[8]^write_addr[8])) then pop is enabling. Here for 8 bit data i am adding an extra bit for checking the overflow condition it is working fine for synchronous. But implementing for asynchronous what i can do?? like adding a grey counter inplace of binary counter (or) adding delay for read_add and write_addr , can you suggest me the best way of doing? Even tell me whether my assumption is correct or not



    •   Alt10th July 2017, 09:33

      advertising

        
       

  6. #6
    Advanced Member level 5
    Points: 34,876, Level: 45
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,391
    Helped
    1862 / 1862
    Points
    34,876
    Level
    45

    Re: Difference b/w asynchronous Vs synchronous FIFO

    Simulink doesnt really handle multiple clock domains, let alone the CDC part of it. You're probably much better off black boxing the CDC fifo and have it instantiate some vendor IP for you.
    And Im pretty sure Simulink provides a FIFO block already..



--[[ ]]--