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Hi,
Is it possible to get 8 bit input data with 25 Mhz frequency and convert the data after 6 cycle to 48 bit output data at 20 Mhz frequency using x95 CPLD families?
If your input data rate is 8 bits with 25MHz....and you convert it to 48bit wide..then it is exactely with 4.1667MHz averaged.
You may have burst with 20MHz, but thats a problem of a FIFO buffer.
Are both clocks generated from the same clock source...and therefore they can be considered to be synchronous every 5th/4th clock?
Or are the not synchronous at all.
If not synchronous: Who is generating both clocks and how do you ensure they come to exactely the same data_bit_rate?
Please show a diagram of your data flow with all involved signals.
input and output clk are synchronous and I should create 20 Mhz clk from the input clk. Input clk come from external 25 mhz oscillator. In fact, I want to obtain 48 bits data with 20 Mhz from 8 bits input data with 25 Mhz frequency. I was wondering if it's possible to use a buffer to handle difference rate of input and output? In addition, can I use pll to make 20 Mhz clk fom 25 Mhz in CPLD?
I inset an image too.
The data assignment shown in the picture doesn't fit a 20 MHz output rate unless you implement an interpolation filter. You also need a FPGA series with PLL, XC95 doesn't provide it.
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