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Hello,
The way you do it is called "SYNTHESIS". you've different tools in the market to do synthesis.
The only way you do it manually is to replace all your cells in the module with the particular std.cells from your desired library. This will be hectic for larger modules.
Hi Kahsh,
Thanks for your reply, yah I understand synthesis very well. May be I did not make my point clear. I want to force the synthesis tool to use specific standard cell to map one of my modules. Think about it as calling one standard cell early in the front end coding.
Thanks
Let the normal synth flow take place.
You will get the netlist file.
Write a script that reads in your netlist, searches for the modules that needs to be replaced, replaces it with the desired standard cell.
In the case of Synopsys Design Compiler as your synthesis tool:
You can use "set_dont_use" command to filter out any std-cells you don't want to use during synthesis. For example "set_dont_use MAXLIB/INVX1" will bar synthesis tool from using INVX1 inverter from MAXLIB library.
Knowing how to control which cells to use (or not use), you can synthesize your module with most of the cells set as dont_use (leaving out the ones you want). After that, synthesize the rest of your design (using none of those set_dont_use script) with that module marked as "dont_touch". I figure this will get what you want.
set_dont_use is the way to go. you can use wildcard with it, so first you can block all cells from being used with set_dont_use * true, and later you can enable the ones you want one by one with set_dont_use my_prefered_inverter false
Thank you guys! All solutions looks valid for me. However, I wonder if I can find more straightforward solution. Can I name the module exactly as the standard cell name? Do you think this will make the synthesis tool use this standard cell for mapping? I am really shocked when I figured out that HDL (VHDL, Verilog) don't have a way to use specific standard cell early in the front end code !!!
Thank you guys! All solutions looks valid for me. However, I wonder if I can find more straightforward solution. Can I name the module exactly as the standard cell name? Do you think this will make the synthesis tool use this standard cell for mapping? I am really shocked when I figured out that HDL (VHDL, Verilog) don't have a way to use specific standard cell early in the front end code !!!
But I think its not a good idea to use different std.cells in the design. Because, if most of your blocks are 2v std.cells and one of the module has 5v std.cells, How can you make sure that the right amount of voltage is passing through. Maybe you might not get the correct functionality on silicon. You need to build level shifters to convert 2v to 5v and feed the 5v module and its output should be down converted from 5v to 2v again. Seems to be a hectic task.
But I think its not a good idea to use different std.cells in the design. Because, if most of your blocks are 2v std.cells and one of the module has 5v std.cells, How can you make sure that the right amount of voltage is passing through. Maybe you might not get the correct functionality on silicon. You need to build level shifters to convert 2v to 5v and feed the 5v module and its output should be down converted from 5v to 2v again. Seems to be a hectic task.
this makes no sense. standard cells have a range of valid vdd values, usualy something like nominal vdd +-10%. 2v and 5v is just not happening in any design, ever. even for extreme low power logic, I have seen modules that operate at 0.55V while some other parts of the system work at 0.8V. But the cells are the same in both modules, they just happen to be powered at different vdd values. whatever the OP does to instantiate his preferred cell directly in the code, does not affect the power intent of the chip or of the module in any way I can think of.
Hi Not Sam
This is exactly what I want to do, structural for some part and RTL for the rest of the design. Now, could you teach me how exactly I can instantiate a standard cell in my HDL code? Let's assume that I have a cell called "XYZ", with "A&B" inputs and "C" output. How I can instantiate this in my HDL to map an entity called "My_HW", taking into consideration that I will use later "My_HW" to build a bigger module in structural fashion let's assume it is called "My_Sys" which contains many of "My_HW". Hope I could make my issue clear.
Thanks for the help
Tiger ... really Tiger
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