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  1. #1
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    How to define clock and reset pins in ZedBoard (Zynq-7000)

    Dear all,


    I have a top file with the following input and output signal:

    INPUTS:
    ----------
    sys_clk
    reset
    cut 1 bit (if '1', the signal ceases)
    start 1 bit (if '1', the design works)
    enable 1 bit (if '1', the design and clock is fed to design)

    OUTPUTS:
    -------------
    done 1 bit (end of action flag)
    ready 1 bit (ready flag for transmission)



    As I looked at the ZedBoard manual in the attachment, the 100 MHz on-board clock signal is on pin Y9, and I want to use DIP switches for cut, start, enable signal (F22, G22, H22) and a push button (BTNC) for reset.

    I defied the following constraint in my .XDC file:

    create_clock -name sys_clk -period 10 [get_ports sys_clk]
    where sys_clk is the name of clock signal in my top file that I would like to connect it to pin Y9 to be 100 MHz. But how can I define this constraint in my XDC file? What are the required constraints to be defined for the other signals (DIP switches and push button)??

    Kind replies and helps are in advance appreciated.

    Regards,

    •   Alt5th July 2017, 23:11

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  2. #2
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    Re: How to define clock and reset pins in ZedBoard (Zynq-7000)

    Code:
    set_property iostandard xxxxxx [get_ports sys_clk]
    set_property package_pin y9 [get_ports sys_clk]
    change xxxxx to LVCMOS18, LVCMOS15, LVTTL etc, whatever standard the Vccio is compatible with.


    1 members found this post helpful.

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