Connected vdd first then gnd with power off and the gnd net fried

Hi guys,

I am testing a project fabricated in 130nm technology, with a supply voltage of 1V (Agilent E3631A) and a bypass capacitor of 100nF. I connected Vdd first then gnd when the power supply was off, then turned the supply on and everything connected to gnd seems to be dead. I have a few biasing stages, just nmos transistors diode connected from gnd to their respective pins and none of them works (note: I ckecked for shorts between pins but didn't find any). Contrary to that, I also have pmos (diode connected) biasing stages from Vdd to their respective pins and they all work. Is it possible the ground net was fried when connecting the Vdd first throught the bypass cap? even with the supply off? shouldn't the charge dissipate throughout the metal that covers the entire PCB instead of the gnd net inside the chip?

Thanks,

Ivan

ivapadil said:

I am testing a project fabricated in 130nm technology, with a supply voltage of 1V (Agilent E3631A) and a bypass capacitor of 100nF.
... Is it possible the ground net was fried when connecting the Vdd first throught the bypass cap? even with the supply off?

Click to expand...

Rather unlikely. How are the gates connected? For possible help, better show your schematic!