+ Post New Thread
Results 1 to 14 of 14
  1. #1
    Full Member level 3
    Points: 1,418, Level: 8

    Join Date
    Aug 2013
    Posts
    154
    Helped
    0 / 0
    Points
    1,418
    Level
    8

    Implementing Look up table in FPGA

    Hi,
    How to implement look up table in fpga and what is its purpose in fpga?

  2. #2
    Advanced Member level 3
    Points: 3,955, Level: 14

    Join Date
    Apr 2016
    Posts
    823
    Helped
    153 / 153
    Points
    3,955
    Level
    14

    Re: Implementing Look up table in FPGA

    I will assume you are confusing concepts.

    An FPGA can implement any logic, and the way it does it is by programming its internal look up tables. A simple google search of 'FPGA LUT diagram' will show you how it works. In general, you write code without the need to directly use the lookup tables. Software will do that for you -- translate your code into a bitstream that populates the LUTs.
    Really, I am not Sam.



    •   Alt5th July 2017, 17:05

      advertising

        
       

  3. #3
    Super Moderator
    Points: 231,316, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    39,925
    Helped
    12197 / 12197
    Points
    231,316
    Level
    100

    Re: Implementing Look up table in FPGA

    I guess the question isn't asking about LUT as logic element in FPGAs but how to implement a ROM table e.g. for a sine generator. The term LUT is unfortunately equivocal.


    1 members found this post helpful.

  4. #4
    Advanced Member level 3
    Points: 3,955, Level: 14

    Join Date
    Apr 2016
    Posts
    823
    Helped
    153 / 153
    Points
    3,955
    Level
    14

    Re: Implementing Look up table in FPGA

    I don't know, the question is so poorly phrased that I assume the OP is as naive as my students and got his concepts wrong.
    Really, I am not Sam.



  5. #5
    Full Member level 3
    Points: 1,418, Level: 8

    Join Date
    Aug 2013
    Posts
    154
    Helped
    0 / 0
    Points
    1,418
    Level
    8

    Re: Implementing Look up table in FPGA

    Quote Originally Posted by FvM View Post
    I guess the question isn't asking about LUT as logic element in FPGAs but how to implement a ROM table e.g. for a sine generator. The term LUT is unfortunately equivocal.
    Exactly, you got right. Could you please explain little bit lets say for sine generator?
    As far I know If I take rom as look up table, I need to initilaize with .coe file but I don't know how to generate corresponding .coe file? Can I also use Block RAM for this purpose?
    Last edited by beginner_EDA; 5th July 2017 at 20:07.



  6. #6
    Super Moderator
    Points: 26,525, Level: 39
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    6,030
    Helped
    1477 / 1477
    Points
    26,525
    Level
    39

    Re: Implementing Look up table in FPGA

    I hope you know that Xilinx and Altrea both have documentation and that documentation tells you how to implement a ROM in their devices.
    Altera: https://www.altera.com/en_US/pdfs/li...ug_ram_rom.pdf
    Xilinx: https://www.xilinx.com/support/docum...lk-mem-gen.pdf
    https://www.xilinx.com/itp/xilinx10/...ngle_block.htm

    MIF format: http://quartushelp.altera.com/15.0/m...ry/def_mif.htm
    COE format: https://www.xilinx.com/support/docum...ile_syntax.htm

    I would think going to the documentation is much more efficient use of your time than posting questions (that are easy to find in the documentation) on edaboard and waiting for answers and then having to explain your vague question until you have a question that can be answered.


    1 members found this post helpful.

    •   Alt5th July 2017, 20:40

      advertising

        
       

  7. #7
    Full Member level 3
    Points: 1,418, Level: 8

    Join Date
    Aug 2013
    Posts
    154
    Helped
    0 / 0
    Points
    1,418
    Level
    8

    Re: Implementing Look up table in FPGA

    Hi ads-ee,
    this is not what I am asking

    https://www.xilinx.com/support/docum...ile_syntax.htm

    but how I know What will be the value of sine generator(certain functionality we want to implement) to put into
    memory_initialization_vector= ?

    DO I need some other tools to generate these values for certain functionality lets say sine generator in this case before assigning to
    memory_initialization_vector=
    ?



  8. #8
    Super Moderator
    Points: 231,316, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    39,925
    Helped
    12197 / 12197
    Points
    231,316
    Level
    100

    Re: Implementing Look up table in FPGA

    Lock-up tables above a certain size will be always implemented in block RAM (ROM is just another name for initialized block RAM in terms of FPGA design).

    Usual options are
    - generating the initialization file (e.g. *.coe) in a spread sheet calculator or math tool.
    - describing the look up table completely in VHDL or Verilog, including the calculation of sine values at synthesis time

    You need to follow specific design templates to get the behavioral table description implemented in block RAM.


    2 members found this post helpful.

  9. #9
    Advanced Member level 2
    Points: 4,182, Level: 15

    Join Date
    Feb 2015
    Posts
    689
    Helped
    208 / 208
    Points
    4,182
    Level
    15

    Re: Implementing Look up table in FPGA

    A classic LUT example is bitcounting. It's not the best example, but it is an interview question.

    In the example question, a 16 bit value is provided and the goal is to count the number of 1's.

    Two LUT-based designs are immediately obvious. The first uses 8bit address to 4 bit output LUTs and then sums the outputs. 4*256b LUT + 4*256b + 4 bit adder. The second uses a 16bit address and 5 bit output for 5*64k bits of LUT. This is an interview question you can ask.

    The 8b luts map 0000_0000 to 0, 0000_0001 and 0000_0010 to 1, 0000_0011 to 2, etc... 1111_1111 gets mapped to 8.

    This is actually a terrible interview question as non-LUT based approaches are likely to be faster in HW or SW. That said, if someone knows or questions the LUT based approach it is a bonus.

    If you actually care about sine waves, look up the Xilinx DDS coregen guide. That explains how you should actually do things.



  10. #10
    Full Member level 3
    Points: 1,418, Level: 8

    Join Date
    Aug 2013
    Posts
    154
    Helped
    0 / 0
    Points
    1,418
    Level
    8

    Re: Implementing Look up table in FPGA

    Hi FvM,
    Thank you.
    Quote Originally Posted by FvM View Post
    - generating the initialization file (e.g. *.coe) in a spread sheet calculator or math tool.
    This you mean like using MATLAB or MS EXCEL?

    Quote Originally Posted by FvM View Post
    You need to follow specific design templates to get the behavioral table description implemented in block RAM.
    one thing is still not clear to me.
    Let's say I have generated a .coe file for sine using matlab/excel that have 32 points i.e. "memory_initialization_vector=" contains 32 different values.
    This look up table can not be used for sine having more than 32 points?

    Quote Originally Posted by FvM View Post
    - describing the look up table completely in VHDL or Verilog, including the calculation of sine values at synthesis time
    This I didn't understand.



    •   Alt8th July 2017, 16:05

      advertising

        
       

  11. #11
    Super Moderator
    Points: 231,316, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    39,925
    Helped
    12197 / 12197
    Points
    231,316
    Level
    100

    Re: Implementing Look up table in FPGA

    Let's say I have generated a .coe file for sine using matlab/excel that have 32 points i.e. "memory_initialization_vector=" contains 32 different values.
    This look up table can not be used for sine having more than 32 points?
    You can generate finer resolution by linear interpolation. Or implement the table with required number of points. Having 1024 to 4096 points is no problem with mid range FPGA. Or use the sine tables provided by FPGA vendor DDS cores. They are using different "hybrid" methods with optimized memory or logic utilization.

    This I didn't understand.
    Many previous posts are discussing sine table calculation in HDL, see e.g.
    http://www.edaboard.com/showthread.p...l=1#post841972


    1 members found this post helpful.

  12. #12
    Full Member level 3
    Points: 1,418, Level: 8

    Join Date
    Aug 2013
    Posts
    154
    Helped
    0 / 0
    Points
    1,418
    Level
    8

    Re: Implementing Look up table in FPGA

    Hi FvM,
    Thank you for the concept.

    This method works for 1D Lookup Table.

    For 1D look up table:
    let's say contents of .coe file for a block memory of depth=16, and width=8 is:
    memory_initialization_radix=16;
    memory_initialization_vector=
    ff,
    ab,
    f0,
    11,
    11,
    00,
    01,
    aa,
    bb,
    cc,
    dd,
    ef,
    ee,
    ff,
    00,
    ff;

    to read/access data all I need is to provide corresponding address of block RAM.

    Now just for curiosity:
    how the format of .coe file looks like for 2D look up table?
    and how to access it in FPGA?

    Similarly for 3-D and so on?



  13. #13
    Advanced Member level 2
    Points: 4,182, Level: 15

    Join Date
    Feb 2015
    Posts
    689
    Helped
    208 / 208
    Points
    4,182
    Level
    15

    Re: Implementing Look up table in FPGA

    any other format is converted into a linear, 1d address. Either unpacked or packed

    packed:
    r1c1 r2c1 r3c3 r2c1 r2c2 r2c3 r3c1 r3c2 r3c3

    unpacked:
    r1c1 r2c1 r3c3 0 r2c1 r2c2 r2c3 0 r3c1 r3c2 r3c3 0 0 0 0 0

    For FPGAs, where the resources already exist, an unpacked representation allows you to compute the address using 2 bit row as 2 msb, and 2bit column as 2 lsb. When the grid is large enough to use several resources, packing can be used. In this case the address needs to be computed as 3*row + col in HW before being provided to the RAM.

    The same for higher dimensions. For a 3x4x5 space, a packed version would have addr = 4*5*x + 5*y + z, assuming x is 0:2, y is 0:3, z is 0:4.



  14. #14
    Advanced Member level 2
    Points: 3,640, Level: 14

    Join Date
    Apr 2011
    Posts
    511
    Helped
    24 / 24
    Points
    3,640
    Level
    14

    Re: Implementing Look up table in FPGA

    Please remember that in case you want to have sinusoidal values and don't have enough logic resources for the whole look up table, an alternate is to use CORDIC. It is a very neat algorithm.



--[[ ]]--