Unable to understand timing diagram of a digital ckt

[hobbyiclearner]

Hi,

I was going through a ckt in Pedroni’s FSM book’s solution manual and was facing problems in its analysis. Hope, someone can help.

In the ckt shown in the picture, the output q of the flip flop is shown to be shifted by one clock cycle (the first rising edge of input x(d)) whereas my understanding is that output will be updated as soon as the input changes. This here is crucial as it will change the entire working of this ckt. Hence, pls. advise.

Thanks,
Hobbyicleaner

[TrickyDicky]

D transfers to the Q output only on the rising edge of the clock, hence the 1 clock delay. This is how flip flops work.
The timing diagram is correct as per the circuit diagram.

[FvM]

By nature of DFF, it's output changes only during the active clock edge. In so far the circuit behavior is as expectable.

I suggest to start the text book literature with the first chapters explaining DFF operation.

[hobbyiclearner]

OK... In that case pls. consider another question from the same chapter exercise solution where the functional response (left diagram) and timing response (right diagram) of a D flip flop are drawn. In both the cases, the output q is changing immediately on rising edge of clock with input d (the delays tpcq are shaded in grey colour in the right diagram). BTW, just to be clear, the delay between the rising edge of clock and the input x(d) of the snapshot in #1 is just tpcq.

Regards,
Hobbyiclearner

[TrickyDicky]

What is the question? The diagrams are correct. The left diagram shows the simulation waveform with no inertial delay. The second diagram is what will occur on real hardware.

The Q output takes the D output on the rising edge of the clock. D is likely to change the clock before. Maybe that is your confusion?

[hobbyiclearner]

My question is.. in D Flip flop, will the change in input be reflected at the output during the same positive clock edge or next positive clock edge? As per diagram in post 1, the output is changing as per the input in the next positive clock edge but as per the diagrams in post 4, the output is changing as per the input in the same positive clock edge (ignoring delays).

Regards,
Hobbyicleaner

[TrickyDicky]

stop thinking about "same" and "next".
Basically, on rising edge of clock, Q becomes whatever D is at that moment in time. There is no difference between the two diagrams, other than the inertial delay caused by circuit delays.

[hobbyiclearner]

OK... then for the first diagram, at the rising edge of the clock, since the input was low (due to delay in change of input), the output was logic zero and so on. For the second diagram, the output changed as per the input during the rising edge of the clock after the tcpq delay (delay between clock edge arrival and output q arrival). Hope this explanation of the diagrams is correct. And yes, thanks for your patience.

Hobbyiclearner

[vGoodtimes]

The diagram in post 4 intends to show that the input to the FF can change at any time during the cycle. It is only the input value at the instant of a rising edge that matters. In this case, the input changes multiple times within a clock cycle. This is to show that the output is only based on the value of the input at the instant of the rising edge.