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doubt in fpga terminal program

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dipin

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serial port demo program working.. but nothing in terminal

hi,

i am trying to do hello world program mentioned in below video..

https://www.youtube.com/watch?v=yEtVLTB4hM4


but i got a problem with rx and tx pin assignment..at 4.45 in video. i am using quartus prime 16.0. here the below mentioned pins are not assignable.
so i tried by assigning only clock, but in terminal after running program nothing is displaying. so i think its because of not assigning the pins for tx and rx. anybody know how to solve this problem ?

Signal Name FPGA Pin No. Description I/O Standard

HPS_UART_RX PIN_B25 HPS UART Receiver 3.3V
HPS_UART_TX PIN_C25 HPS UART Transmitter 3.3V
HPS_CONV_USB_n PIN_B15 Reserve 3.3V

the above one is from user manual of cyclone 5 sockit .(you can get it from google it & first result and then page 38)

so anybody know how to do it . any help is really appreciated

tthanks
 

Re: serial port demo program working.. but nothing in terminal

If the pins are not assignable then maybe you've got a different package than the demo references...
 
Re: serial port demo program working.. but nothing in terminal

hi,
those pins are belong to hps..

regards
 

hi,

did altera cyclone 5 sx fpga will work with terminal program ( like putty, teraterm) with out booting linux from sd card?

like "hello world" program works in cyclone 2 fpga ?

trying to print hello world , didnt get a reference program with soc kit, there is two demos, one is using jtag uart and other one is booting from sd card.

thanks and regards
 

Hi,

If
* the FPGA output is UART style
* the voltage levels and polarity is correct
* the baudrate is correct
* the transmit parameters (usually "8N1") are correct
...Then it should work

Klaus
 
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    dipin

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As said in #2 terminal programs ( like putty, teraterm) are independent of FPGA dev boards.
If your RTL simulation is working properly, just check out the proper settings of the terminal programs.
 
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    dipin

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Not clear what you want to achieve. JTAG UART provides a terminal interface through the Altera JTAG stack, but as far as I know, doesn't provide a virtual COM port that can be accessed by a PC terminal program.

I would expect a real UART implemented in FPGA, connected to a RS-232 driver of the eval board (or possibly throughly an USB bridge).

Secondly, how do you want to implement "Hello world"?. By a OS-less ("bare metal") SOC program? Or in pure HDL?
 
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    dipin

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hi,

i am using nios2 processor + rs232(serial port) + onchip ram. my baud rate is 115200 in both uart and terminal. i tried ttwo terminal, putty and teraterm.

still not able to get it ..i will post my full project here .. what i done is generated qsys system and wrote a wrapper for it
Code:
module uart_top ( clk,tx,rx);

input clk;
input rx;
output tx;

	uart_qsys u0 (
		.clk_clk       (clk),       //     clk.clk
		.reset_reset_n (1'b1), //   reset.reset_n
		.rs232_0_RXD   (rx),   // rs232_0.RXD
		.rs232_0_TXD   (tx)    //        .TXD
	);

endmodule

following is the pin assignments pinplanner.JPG

after that i went to eclipse and create the project and bsp files, then run it n hardware configuration. its showing download to fpga successful but nothing showing in terminal.


i got a doubt about pisnassignment, rx and tx are not able to assign in pinplannerfpgapin.JPG. so after few searching i selected 3.3 ltvvt in i/o part

can any body help me on this please

regards

regrds
 
Last edited:

I don't use Altera, so will not comment on the pin assignment correctness.

But 1 point regarding your uart_qsys u0 instiantiation.
This statement .reset_reset_n (1'b1), // reset.reset_n indicates that uart_qsys is always in non-reset state. But it might need a LOW to HIGH going transition for proper functioning. So please review the uart_qsys docu as to how the reset should actually be.
 
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    dipin

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hi,
below is my full project.

ATTACH]139787[/ATTACH]

teraterm is recognizing my port, in tera teram i am selecting serial port which is already detected by teraterm (com 12) and then open the teramterm, then
>> setup>> serial port>> set baudrate to 115200.

this is how i doing it but it was not a success :(

so can you guys please check my project above ?

regards

- - - Updated - - -

I don't use Altera, so will not comment on the pin assignment correctness.

But 1 point regarding your uart_qsys u0 instiantiation.
This statement .reset_reset_n (1'b1), // reset.reset_n indicates that uart_qsys is always in non-reset state. But it might need a LOW to HIGH going transition for proper functioning. So please review the uart_qsys docu as to how the reset should actually be.

hi i tried it by connecting the reset to slide switch in fpga. but when the switch is in low, the eclipse is throwing the error(during running as hardware), when i made it high eclipse is running fine but nothing on the terminal :(

regards
 

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