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  1. #1
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    ADC with Qsys tool Altera

    Hello friends!

    Since I need to add an ADC in a FPGA project (MAX 10, quartus 17) I tried to donwload some example from altera cloud, like the one below:

    https://cloud.altera.com/devstore/pl...monitor-panel/

    After compilation quartus reports that no logic depends on input clock (to ADC) and that all pin connected to tha ADC dataout are stacked@gnd.

    No ADC example from altera cloud help me, always the same problem...

    Can somebody help me in this trip? I'm new in FPGA programming and I can't understand why I'm wrong..

    Thanks in advance,

    Regards!

    •   Alt3rd July 2017, 15:30

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  2. #2
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    Re: ADC with Qsys tool Altera

    Quote Originally Posted by grezzoman View Post
    I'm new in FPGA programming and I can't understand why I'm wrong..
    And I can't understand what your question is, nor do you supply any useful information to help answer your question (whatever the question is supposed to be).



    •   Alt5th July 2017, 22:13

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  3. #3
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    Re: ADC with Qsys tool Altera

    you can use a microcontroller to read the analog input then feed it to the FPGA/CPLD

    if you don't want that solution, you can buy a ADC IC and interface with it.



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