Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

LDPC decoder in verilog- Problem with BER computation

Status
Not open for further replies.
N

NikosTS

Advanced Member level 4
Joined
Jan 30, 2017
Messages
119
Helped
1
Reputation
2
Reaction score
2
Trophy points
18
Activity points
1,054
Hello everyone,
I have designed an LDPC decoder for 802.11n standard ( code 1944 ), using min sum algorithm. I am trying to compute the BER performance over different values of SNR.
So, at each decoding iteration, i compare the temporary decoded codeword with the original one and sum the number of unequal bits.
Problem is that instead of the errors becoming fewer after every iteration, they become more. Also, different SNR levels seem to have no impact on the BER as i constantly get around 0.5-0.6.
Any suggestions as to what could have gone wrong?

Thank you in advance,
Nikos
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top