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Matrix array inside a for loop VHDL

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nizdom

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Hi guys. I wanted to make a matrix array that is created inside a for loop. It's like in every loop, a different matrix array is created.

Here is a portion of my code. This part is when the matrix is updated and incremented.

Code:
IF(CLK'EVENT AND CLK = '1') THEN	
		FOR I IN 0 TO PORT_SIZE-1 LOOP
			IF(START_RX(I) = '1')THEN
				PORT_RX(I) := TO_INTEGER(UNSIGNED(RX_MATRIX(I)(1 DOWNTO 0))); 			-- GET PORT ADDRESS
                                PORTMATRIXA(I)(PORT_RX(I)) <= PORTMATRIXA(CARD_RX)(PORT_RX(I)) + 1;  -- INCREMENT MATRIX POSITION
	
			 END IF;

In here, for example, for 0 to 3, for every loop, I want to create a different matrix so at the end of all the loops, I can have 4 different matrix array with integer values. so PORTMATRIXA would consist of 4 arrays with integer values. What would be my declaration types? Any help?
 

Im not quite sure I understand your question? Can you please post all of the code, and try and explain better what the problem is?
In your code, if Start_rx(I) = '1' then PORTMATRIXA(I) will be updated with new values.
 

The code doesn't make sense to me either.

In terms of declarations, the two options are to declare a multi-dimensional array of integer, ideally with a range specification. The second option is to describe and array of arrays of integers, ideally with a range specification. The latter is done because tools are known to support this for synthesis. It also avoids confusion with attributes that need a dimension index for the multi-dimensional array type.

this SO link does a good job describing this: https://stackoverflow.com/questions/30651269/synthesizable-multidimensional-arrays-in-vhdl

and you might want to replace std_logic_vector with integer, or integer range -128 to 127, or whatever size you want. (>32b int should use unsigned/signed with the appropriate number of bits).

- - - Updated - - -

The code doesn't make sense to me either.

In terms of declarations, the two options are to declare a multi-dimensional array of integer, ideally with a range specification. The second option is to describe and array of arrays of integers, ideally with a range specification. The latter is done because tools are known to support this for synthesis. It also avoids confusion with attributes that need a dimension index for the multi-dimensional array type.

this SO link does a good job describing this: https://stackoverflow.com/questions/30651269/synthesizable-multidimensional-arrays-in-vhdl

and you might want to replace std_logic_vector with integer, or integer range -128 to 127, or whatever size you want. (>32b int should use unsigned/signed with the appropriate number of bits).
 

It is like I wanted to make PORTMATRIXA consist of four arrays with integer values. So I can have, PORTMATRIXA(0) = 1 2 4 12 4 12 34 43, PORTMATRIXA(1) = 12 7 3 12 44 12 4 2 and so on. in which each array is created inside the FOR LOOP.
 

I dont think you mean created, I think you mean assigned.
Why not post the code you think is correct, and we can see what the problem is? At the moment, the code you posted doesnt really have any link to what you are asking..
 

What would be my type declaration for CARD_MATRIX if I wanted to make it as an output in my port declaration? would it be integer?

Code:
TYPE CARD_MATRIX IS ARRAY (0 TO PORT_SIZE-1, 0 TO 7) OF INTEGER RANGE 0 TO 256;
SIGNAL CARD_MATRIXA : CARD_MATRIX;
 

card_matrix is a type, so it is alreaduy a type.
 

This is the entity block I am working on. This is only one of the entity blocks I am working on. I am having problems with declaring CARD_MATRIXB as an output in the PORT Declarations.

Code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE WORK.TSS_4PORT_PKG.ALL;

ENTITY VOQ_MATRIXX IS
	PORT (
		CLK, ENABLE, RESET 		    			: IN STD_LOGIC; 											--! CONTROL SIGNALS
		WRT_MATRIX			      				: IN STD_LOGIC_VECTOR(PORT_SIZE-1 DOWNTO 0); 						--! SIGNAL INFORMING THE MATRIX THAT IT WILL BE UPDATED.
		RX_MATRIX					    			: IN MATDATA_TYPE; 											--! HEADER DATA FROM RX THAT WILL BE INCREMENTED.
		CUT_MATRIX				     				: IN STD_LOGIC_VECTOR(PORT_SIZE-1 DOWNTO 0); 						--! DECRIMENT MATRIX COUNT 
		TX_MATRIX                   			: IN MATDATA_TYPE; 											--! HEADER DATA FROM FETCH THAT WILL BE DECREMENTED.
		CARD_MATRIXB					    		: OUT CARD_MATRIX(0 TO PORT_SIZE-1)(0 TO 7)		--! INTEGER ARRAY HOLDING THE VALUE OF THE MATRIX ARRAY USED REPRESENTING THE LENGTHOF QUEUES PER INPUT PORT FOR CARD 1.
	);
	
END VOQ_MATRIXX;

-- MATDATA_TYPE 16 ADDRESS WITH 8 BINARY LENGTH
-- PORTMATRIX_TYPE 256 ADDRESS WITH INTEGER RANGE 0 - 4095


ARCHITECTURE BEHAVIOUR OF VOQ_MATRIXX IS
	
	SIGNAL START_RX 		     				: STD_LOGIC_VECTOR(PORT_SIZE-1 DOWNTO 0) := (OTHERS=>'0'); 			--! USED TO DETECT THE POSITIVE EDGE OF EACH INCREMENT REQUEST
	SIGNAL START_RX_N 		     				: STD_LOGIC_VECTOR(PORT_SIZE-1 DOWNTO 0) := (OTHERS=>'0'); 			--! USED TO DETECT THE POSITIVE EDGE OF EACH INCREMENT REQUEST
	SIGNAL START_TX 		     				: STD_LOGIC_VECTOR(PORT_SIZE-1 DOWNTO 0) := (OTHERS=>'0'); 			--! USED TO DETECT THE POSITIVE EDGE OF EACH DECREMENT REQUEST
	SIGNAL START_TX_N 		     				: STD_LOGIC_VECTOR(PORT_SIZE-1 DOWNTO 0) := (OTHERS=>'0'); 			--! USED TO DETECT THE POSITIVE EDGE OF EACH DECREMENT REQUEST
	 	
	
	TYPE TXHEAD_TYPE IS ARRAY (0 TO PORT_SIZE-1) OF STD_LOGIC_VECTOR(3 DOWNTO 0); 									--! OUTPUT HEADER PORT_SIZE - 1
	SIGNAL TX_HEAD 							: TXHEAD_TYPE; 												--! CHECKS THE VALUES OF THE HEADER. SIMULATION DUMMY.
	SIGNAL TX_OUTPUT 							: INTEGER_ARRAY4 := (OTHERS => 0);							--! TRACKS THE DECRIMENTS PER PORT
	
	TYPE CARD_MATRIX IS ARRAY (0 TO PORT_SIZE-1, 0 TO 7) OF INTEGER RANGE 0 TO 256;     --! MATRIX ARRAY FOR COLOR-CARD
	SIGNAL CARD_MATRIXA : CARD_MATRIX;
	
BEGIN	
CARD_MATRIXB <= CARD_MATRIXA;
--PROCESSES
	REQUEST_EDGE: PROCESS (CLK)
	BEGIN
		IF (CLK'EVENT AND CLK = '1') THEN	
			FOR I IN 0 TO PORT_SIZE-1 LOOP
				START_RX_N(I) <= NOT (WRT_MATRIX(I));
				START_RX(I) <= (START_RX_N(I) AND WRT_MATRIX(I));
				START_TX_N(I) <= NOT (CUT_MATRIX(I));
				START_TX(I) <= (START_TX_N(I) AND CUT_MATRIX(I));
			END LOOP;
		END IF;
	END PROCESS REQUEST_EDGE;
	
	UPDATING: PROCESS(CLK, RESET)
		VARIABLE PORT_RX : INTEGER_ARRAY4; 									-- HAS RANGE OF 16 ADDRESS WITH 0-15 VALUES
		VARIABLE PORT_TX : INTEGER_ARRAY4;
		BEGIN
		
		IF (RESET = '0') THEN
			CARD_MATRIXA <= ((OTHERS=>0)); 
		ELSE
			IF(CLK'EVENT AND CLK = '1') THEN	
				FOR I IN 0 TO PORT_SIZE-1 LOOP
					IF(START_RX(I) = '1')THEN
						PORT_RX(I) := TO_INTEGER(UNSIGNED(RX_MATRIX(I)(1 DOWNTO 0))); 							-- GET PORT ADDRESS
						IF (RX_MATRIX(I)(4) = '0') THEN
							CARD_MATRIXA(I,PORT_RX(I)) <= CARD_MATRIXA(I,PORT_RX(I)) + 1;  -- INCREMENT MATRIX POSITION
						ELSE
							CARD_MATRIXA(I,PORT_RX(I)+PORT_SIZE) <= CARD_MATRIXA(I,PORT_RX(I)+PORT_SIZE) + 1;  -- INCREMENT MATRIX POSITION
						END IF;
					END IF;
					
					IF(START_TX(I) = '1') THEN
						PORT_TX(I) := TO_INTEGER(UNSIGNED(TX_MATRIX(I)(1 DOWNTO 0))); 							-- GET PORT ADDRESS
						IF (TX_MATRIX(I)(4) = '0') THEN
							CARD_MATRIXA(I,PORT_TX(I)) <= CARD_MATRIXA(I,PORT_TX(I)) - 1;  -- DECREMENT MATRIX POSITION
						ELSE
							CARD_MATRIXA(I,PORT_TX(I)+PORT_SIZE) <= CARD_MATRIXA(I,PORT_TX(I)+PORT_SIZE) - 1;  -- DECREMENT MATRIX POSITION
						END IF;
					END IF;
				END LOOP;
			END IF;
		END IF;

	END PROCESS UPDATING;
	END BEHAVIOUR;

- - - Updated - - -

Basically what it does, depending on an 8-bit data, the count in a certain position in the matrix array is incremented (then decremented after a certain timeslot which happens at the latter part of the process in the whole project). What I wanted to happen is to output the matrix array so I can map it to the next entity block. The error when I compile it says that CARD_MATRIX is used but not declared.
 

What would be my type declaration for CARD_MATRIX if I wanted to make it as an output in my port declaration? would it be integer?

Code:
TYPE CARD_MATRIX IS ARRAY (0 TO PORT_SIZE-1, 0 TO 7) OF INTEGER RANGE 0 TO 256;
SIGNAL CARD_MATRIXA : CARD_MATRIX;

Can we see your port declaration?

What you need to understand with vhdl is there are two ways of doing a multidimensional array

There is
1. A true multidimensional array
type a is array (dimension_1_range, dimension_2_range, dimension_3_range) of [type]
Under this instance you address the array with the following
a(dimension_1_location, dimension_2_location, dimension_3_location) - This will return the type constained in that location

2. Is a multidimensional array made up of many 1d arrays. Think of this as a structure.
type a2 is array(range) of [type2]
type a3 is array(range) of [type a2]


I would do one better than #3 and recommend our own site
Please read the following
https://www.edaboard.com/showthread.php?t=30735&p=1347958#post1347958


To touch on making an array or growing it. You will find that it is assigned during synthesis and compilation/elaboration.

What exactly do you want to achieve?
It is like I wanted to make PORTMATRIXA consist of four arrays with integer values. So I can have, PORTMATRIXA(0) = 1 2 4 12 4 12 34 43, PORTMATRIXA(1) = 12 7 3 12 44 12 4 2 and so on. in which each array is created inside the FOR LOOP.

What you have quoted here is
INTEGER_ARRAY IS ARRAY (0 TO 7) OF TYPE INTEGER;
PORTMATRIX IS ARRAY (0 TO X) OF TYPE INTEGER_ARRAY;
PORTMATRIX(0) = (1, 2, 4, 12, 4, 12, 34, 43)
PORTMATRIX(0)(2) = 2
 

CARD_MATRIXB : OUT CARD_MATRIX(0 TO PORT_SIZE-1)(0 TO 7)

If CARD_MATRIX is declared as above, then you're declaraing it wrong. It has already been decalred with sizes in the type definitiion.
 

If CARD_MATRIX is declared as above, then you're declaraing it wrong. It has already been decalred with sizes in the type definitiion.

So how can I make the matrix array assigned to CARD_MATRIX as an output in the port declaration? Any idea?
 

It is declared as an output. But the type already has a fixed size - you cannot resize it in the port declaration.
 

More direct -- remove the sizes. Just use "CARD_MATRIX" instead of "CARD_MATRIX(range,range)"

also, you have a range of 0 to 256. This is a 9 bit value. You probably wanted either 0 to 255 or 0 to 511.
 

More direct -- remove the sizes. Just use "CARD_MATRIX" instead of "CARD_MATRIX(range,range)"

also, you have a range of 0 to 256. This is a 9 bit value. You probably wanted either 0 to 255 or 0 to 511.

Error says "object "CARD_MATRIX" is used but not declared"
 

To use a type for the entity ports, it must be declared in an external package, e.g. TSS_4PORT_PKG, not in the entity body itself. Apparently you don't.
 

I have already included the CARDMATRIX_TYPE in the package. Now the error says CARD_MATRIXA does not agree with its usage as CARDMATRIX_TYYPE. Can someone help me find out why? Like I have checked it already but I still don't know why. Code is below. PORT_SIZE = 4 in this code.

Code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE WORK.TSS_4PORT_PKG.ALL;

ENTITY VOQ_MATRIXX IS
	PORT (
		CLK, ENABLE, RESET 		    			: IN STD_LOGIC; 											--! CONTROL SIGNALS
		WRT_MATRIX			      				: IN STD_LOGIC_VECTOR(PORT_SIZE-1 DOWNTO 0); 						--! SIGNAL INFORMING THE MATRIX THAT IT WILL BE UPDATED.
		RX_MATRIX					    			: IN MATDATA_TYPE; 											--! HEADER DATA FROM RX THAT WILL BE INCREMENTED.
		CUT_MATRIX				     				: IN STD_LOGIC_VECTOR(PORT_SIZE-1 DOWNTO 0); 						--! DECRIMENT MATRIX COUNT 
		TX_MATRIX                   			: IN MATDATA_TYPE; 											--! HEADER DATA FROM FETCH THAT WILL BE DECREMENTED.
		CARD_MATRIXB					    		: OUT CARDMATRIX_TYPE		--! INTEGER ARRAY HOLDING THE VALUE OF THE MATRIX ARRAY USED REPRESENTING THE LENGTHOF QUEUES PER INPUT PORT FOR CARD 1.
	);
	
END VOQ_MATRIXX;

-- MATDATA_TYPE 16 ADDRESS WITH 8 BINARY LENGTH
-- PORTMATRIX_TYPE 256 ADDRESS WITH INTEGER RANGE 0 - 4095


ARCHITECTURE BEHAVIOUR OF VOQ_MATRIXX IS
	
	SIGNAL START_RX 		     				: STD_LOGIC_VECTOR(PORT_SIZE-1 DOWNTO 0) := (OTHERS=>'0'); 			--! USED TO DETECT THE POSITIVE EDGE OF EACH INCREMENT REQUEST
	SIGNAL START_RX_N 		     				: STD_LOGIC_VECTOR(PORT_SIZE-1 DOWNTO 0) := (OTHERS=>'0'); 			--! USED TO DETECT THE POSITIVE EDGE OF EACH INCREMENT REQUEST
	SIGNAL START_TX 		     				: STD_LOGIC_VECTOR(PORT_SIZE-1 DOWNTO 0) := (OTHERS=>'0'); 			--! USED TO DETECT THE POSITIVE EDGE OF EACH DECREMENT REQUEST
	SIGNAL START_TX_N 		     				: STD_LOGIC_VECTOR(PORT_SIZE-1 DOWNTO 0) := (OTHERS=>'0'); 			--! USED TO DETECT THE POSITIVE EDGE OF EACH DECREMENT REQUEST
	 	
	
	TYPE TXHEAD_TYPE IS ARRAY (0 TO PORT_SIZE-1) OF STD_LOGIC_VECTOR(3 DOWNTO 0); 									--! OUTPUT HEADER PORT_SIZE - 1
	SIGNAL TX_HEAD 							: TXHEAD_TYPE; 												--! CHECKS THE VALUES OF THE HEADER. SIMULATION DUMMY.
	SIGNAL TX_OUTPUT 							: INTEGER_ARRAY4 := (OTHERS => 0);							--! TRACKS THE DECRIMENTS PER PORT
	
	TYPE CARDMATRIX_TYPE IS ARRAY (0 TO PORT_SIZE-1, 0 TO 7) OF INTEGER RANGE 0 TO FIFO_SIZE;     --! MATRIX ARRAY FOR COLOR-CARD
	SIGNAL CARD_MATRIXA : CARDMATRIX_TYPE;
	
BEGIN	
CARD_MATRIXB <= CARD_MATRIXA;
--PROCESSES
	REQUEST_EDGE: PROCESS (CLK)
	BEGIN
		IF (CLK'EVENT AND CLK = '1') THEN	
			FOR I IN 0 TO PORT_SIZE-1 LOOP
				START_RX_N(I) <= NOT (WRT_MATRIX(I));
				START_RX(I) <= (START_RX_N(I) AND WRT_MATRIX(I));
				START_TX_N(I) <= NOT (CUT_MATRIX(I));
				START_TX(I) <= (START_TX_N(I) AND CUT_MATRIX(I));
			END LOOP;
		END IF;
	END PROCESS REQUEST_EDGE;
	
	UPDATING: PROCESS(CLK, RESET)
		VARIABLE PORT_RX : INTEGER_ARRAY4; 									-- HAS RANGE OF 16 ADDRESS WITH 0-15 VALUES
		VARIABLE PORT_TX : INTEGER_ARRAY4;
		BEGIN
		
		IF (RESET = '0') THEN
			CARD_MATRIXA <= ((OTHERS=>(OTHERS=>0))); 
		ELSE
			IF(CLK'EVENT AND CLK = '1') THEN	
				FOR I IN 0 TO PORT_SIZE-1 LOOP
					IF(START_RX(I) = '1')THEN
						PORT_RX(I) := TO_INTEGER(UNSIGNED(RX_MATRIX(I)(1 DOWNTO 0))); 							-- GET PORT ADDRESS
						IF (RX_MATRIX(I)(4) = '0') THEN
							CARD_MATRIXA(I,PORT_RX(I)) <= CARD_MATRIXA(I,PORT_RX(I)) + 1;  -- INCREMENT MATRIX POSITION
						ELSE
							CARD_MATRIXA(I,PORT_RX(I)+PORT_SIZE) <= CARD_MATRIXA(I,PORT_RX(I)+PORT_SIZE) + 1;  -- INCREMENT MATRIX POSITION
						END IF;
					END IF;
					
					IF(START_TX(I) = '1') THEN
						PORT_TX(I) := TO_INTEGER(UNSIGNED(TX_MATRIX(I)(1 DOWNTO 0))); 							-- GET PORT ADDRESS
						IF (TX_MATRIX(I)(4) = '0') THEN
							CARD_MATRIXA(I,PORT_TX(I)) <= CARD_MATRIXA(I,PORT_TX(I)) - 1;  -- DECREMENT MATRIX POSITION
						ELSE
							CARD_MATRIXA(I,PORT_TX(I)+PORT_SIZE) <= CARD_MATRIXA(I,PORT_TX(I)+PORT_SIZE) - 1;  -- DECREMENT MATRIX POSITION
						END IF;
					END IF;
				END LOOP;
			END IF;
		END IF;

	END PROCESS UPDATING;
	END BEHAVIOUR;
 

For clarity, you should not repeat the type declaration in the entity body, just use the declaration from the package.
 

For clarity, you should not repeat the type declaration in the entity body, just use the declaration from the package.

Now I am having an internal error.

Code:
Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/vrfx_verific_elaborator.cpp, Line: 2144
c
Stack Trace:
    0x61d46: VRFX_ELABORATOR::elaborate + 0x8566 
    0x61c87: VRFX_ELABORATOR::elaborate + 0x84a7 
    0x61167: VRFX_ELABORATOR::elaborate + 0x7987 
    0x6041f: VRFX_ELABORATOR::elaborate + 0x6c3f 
    0x599cc: VRFX_ELABORATOR::elaborate + 0x1ec 
    0xc50b3: sgn_clear_check_ip_functor + 0x3aeb3 
    0xc8d7f: sgn_clear_check_ip_functor + 0x3eb7f 
    0xca666: sgn_clear_check_ip_functor + 0x40466 
    0x92834: sgn_clear_check_ip_functor + 0x8634 
    0xa37fc: sgn_clear_check_ip_functor + 0x195fc 
    0xa79ee: sgn_clear_check_ip_functor + 0x1d7ee 
    0x10d12: sgn_qic_full + 0x152 



    0x11fad: qexe_get_command_line + 0x1b7d 
    0x14e0e: qexe_process_cmdline_arguments + 0x59e 
    0x14f21: qexe_standard_main + 0xa1 

     0x4ae8: msg_exe_fini + 0x58 
     0x522c: msg_exe_fini + 0x79c 
     0x1524: MEM_SEGMENT_INTERNAL::~MEM_SEGMENT_INTERNAL + 0x194 
     0x5e0f: msg_exe_main + 0x8f 

     0x8363: BaseThreadInitThunk + 0x13 
    0x670d0: RtlUserThreadStart + 0x20 

End-trace
 

Funny. If internal error occurs, delete db and temp_db directories and perform a clean compilation. If the error persists, you probably have done something really weird.
 

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