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reading from w5300 registers

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farzaneh_2561

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Hi everybody,
I am trying to drive a W5300 chip using FPGA. I was able to write into its registers successfully, but I have problem reading from the registers. Here is the timing description for read operation.

1. I drive cs and rd low. at the same time I put the register address on address bus. rd and cs stay low for 50ns.
2. I read the data bus.
3. cs and rd stay low for another 50ns. address is not changed until cs and rd are high.

but the bus always remains zero. not a change. I monitored the data bus using oscilloscope, but all data lines were zero all the time. Also, I tried reading from different registers.
Am I missing something here?

I really appreciate your help!
 

No, I am using spartan 6 and I used IOBUF primitive to tri-state the data bus.
 

Perhaps W5300 isn't clocked correctly or hold in reset. How do you verify that write access is actually working?
 

I can ping it. I set the MAC Address, IP address, Gateway address and Subnet mask. Using command line I can ping it (tx led blinks) and I receive reply from the specified IP Address.
 

O.K. sounds like writing to W5300 works. Then it's probably some basic error in the FPGA interface implementation.
 

You should post the code for the FPGA read/write interface to the W5300.

Based on your description it sounds like you have ADDR, /CS, /RD all asserted at the same time and they are held for 100 ns and you capture DATA at 50 ns after assertion of those signals. Is that correct?

If so it does match the following waveform and timing parameters from the datasheet.
Capture.PNG

You may be using a IOBUF, but how are you specifically controlling the tristate input?

- - - Updated - - -

I think capturing at the 50 ns point depending on your input/output pin constraints and your clock insertion delay/compensation is optimistic. There is only 8 ns from valid data to when you capture the data, it is doable, but only if you've analyzed the timing and used the correct constraints.
 

Code:
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:15:29 06/18/2017 
-- Design Name: 
-- Module Name:    w5300_config - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
--use STD.textio.all;
use ieee.std_logic_textio.all;

library UNISIM;
use UNISIM.VComponents.all;
use work.AVA6STest_Package.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity w5300_config is
    port 
    (
        
        o_Eth_CS : out  std_logic;
        o_Eth_RD : out  std_logic;
        o_Eth_WR : out  std_logic;
        o_Eth_RST : out  std_logic;
        io_Data : inout  STD_LOGIC_VECTOR (7 downto 0);
        io_Addr_Eth : inout  STD_LOGIC_VECTOR (9 downto 0);
        --o_USB_SLOE : out  STD_LOGIC;
        i_SYS_RESET : in  STD_LOGIC;
    --    x2 : out std_logic_vector (7 downto 0); 
        CLK_in : in  std_logic;
    --    flag : out std_logic;
        CLK_out : out  std_logic
    
    );
end w5300_config;

architecture Behavioral of w5300_config is

signal clk_20,clk_10, Eth_RD : std_logic := '0';
signal delay_cnt : integer := 0;
signal x1 : std_logic_vector (2 downto 0):= "000";
component pll is
port
 (-- Clock in ports
  CLK_IN1           : in     std_logic;
  -- Clock out ports
  CLK_OUT1          : out    std_logic;
  CLK_OUT2               :out       std_logic
 );
end component;

begin

s_Eth_ReConfig <= i_SYS_RESET;

clock_20 : pll port map  ( CLK_in,clk_20,clk_10);
--CLK_out <= clk_20;
io_Addr_Eth <= s_W_ADDR;
--io_Data <= s_W_DATA_Out;

    Inst_Data_IOBUF_Generate :
        for i in 7 downto 0 generate
        begin
            Inst_Data_IOBUF : IOBUF
            generic map (
                --DRIVE => 24,
                IOSTANDARD => "DEFAULT",
                SLEW => "FAST")
            port map (
                O => s_DATA_In(i),     -- Buffer output
                IO => io_DATA(i),   -- Buffer inout port (connect directly to top-level port)
                I => s_DATA_Out(i),     -- Buffer input
                T => s_Data_DIR      -- 3-state enable input, high=input, low=output
            );
        end generate;    

s_DATA_Out <= s_W_DATA_Out; --when s_W_RD_WRB = '0' else s_W_DATA_In_Des;
s_W_DATA_In     <= s_DATA_In;
s_Data_DIR <= s_W_RD_WRB;

--o_USB_SLOE <=  '1';
Wiznet_Config_Process : process(clk_20)
    begin
        if rising_edge(clk_20) then
            o_Eth_RST <= '1';
            s_WriteTrig <= '0';
            s_ReadTrig <= '0';    
            case s_Eth_Config_State is

                when c_Eth_Config_State_Idle =>    
                    s_Idle_cnt <= s_Idle_cnt + 1;
                --    s_Interface_Type <= c_LAN_INTERFACE;
                    s_cnt_Wiznet_Config <= s_cnt_Wiznet_Config + 1;
                    if s_Wiznet_Ini_Reset = '0' then--Reset Cycle Time = 2us ; PLL Lock-in Time = 10ms
                        o_Eth_RST <= '0';
                        if s_cnt_Wiznet_Config > 20000 then    -- 20000 * 50ns = 1ms -- min 2us
                            s_Wiznet_Ini_Reset <= '1';
                            s_cnt_Wiznet_Config <= 0;
                            --o_Eth_RST <= not o_Eth_RST ;--'0';
                        end if;    
                    elsif s_Wiznet_Init_PLL = '0' then
                        if s_cnt_Wiznet_Config > 240000 then    -- 240000 * 50ns = 12ms -- min 10ms
                            s_Wiznet_Init_PLL <= '1';
                            s_cnt_Wiznet_Config <= 0;
                        end if;                        
                    else 
                    --    if s_Idle_cnt = 0 then
                            s_Eth_Config_State <= c_Eth_Config_State_Config1;
                            s_Index1 <= c_WIZNET_INIT_DATA_LENGTH_WR-1;
                            s_Index2 <= 0;
                    --    else

                    --    end if;
                    end if;

                when c_Eth_Config_State_Config1 =>
                    s_W_ADDR_Des         <= c_WIZNET_INIT_ADDR_WR(s_Index1);
                    s_W_DATA_Out_Des    <= c_WIZNET_INIT_DATA_WR(s_Index1);
                    s_WriteTrig <= '1';
                    s_Index1 <= s_Index1 - 1;
                    
                    if s_Index1 > 0 then
                --        s_W_ADDR_Des         <= c_WIZNET_INIT_ADDR_WR(s_Index1);
                --        s_W_DATA_Out_Des    <= c_WIZNET_INIT_DATA_WR(s_Index1);
                        s_Eth_Config_State <= c_Eth_Config_State_Config2;
                        
                        
                    elsif s_Index1 = 0 then
                        --s_Idle_cnt <= s_Idle_cnt + 1;
                --        s_W_DATA_Out_Des    <= x"20";
                    --    S0_CR1 <= x"20";    
                    --    if (r_cnt )
                --        s_Eth_Config_State <= c_Eth_Config_State_Config3;
                        s_Eth_Config_State <= c_Eth_Config_State_delay;
                    --else
                --        s_Eth_Config_State <= c_Eth_Config_State_End;
                    end if;        
                
                when c_Eth_Config_State_Config2 =>    
                    if s_W_DATA_Out_Des_Done = '1' then
                        s_Eth_Config_State <= c_Eth_Config_State_Config1;
                    end if;
                when c_Eth_Config_State_delay =>
                    if delay_cnt < 5 then
                        delay_cnt <= delay_cnt + 1;
                    else 
                        s_Eth_Config_State <= c_Eth_Config_State_Config3;
                    end if;
                when c_Eth_Config_state_Config3 => 
                    --s_W_DATA_Out_Des <= (others => 'Z');
                    
                    s_W_ADDR_Des         <= c_WIZNET_INIT_ADDR_RD(s_Index2);
                    --s_W_DATA_Out_Des    <= c_WIZNET_INIT_DATA_RD(s_Index);
                   s_ReadTrig <= '1';
                    s_Index2 <= s_Index2 + 1;
                    if s_Index2 < c_WIZNET_INIT_DATA_LENGTH_RD-1 then
                        s_Eth_Config_State <= c_Eth_Config_State_Config4;
                    else
                        s_Eth_Config_State <= c_Eth_Config_State_End;
                    end if;    
                when c_Eth_Config_State_config4 =>
                    if s_W_DATA_In_Des_Rdy = '1' then
                        s_Eth_Config_State <= c_Eth_Config_State_Config3;
                    end if;

                when c_Eth_Config_State_End =>                        
                    s_Eth_Config_State <= c_Eth_Config_State_End;
                --    s_Interface_Type <= c_USB_INTERFACE;
                    if s_Eth_ReConfig = '0' then
                        s_Wiznet_Ini_Reset <= '0';
                        s_Wiznet_Init_PLL <= '0';
                        s_Eth_Config_State <= c_Eth_Config_State_Idle;
                    end if;
                        
                    
                when others =>
                        s_Eth_Config_State <= c_Eth_Config_State_Idle;
                            

            end case;                

        end if;
    end process;

-----------------------------------------------------------------------------------
WiznetReadWrite_Process : process(clk_20)
    begin
        if rising_edge(clk_20) then

            case s_Eth_RW_State is

                when c_Eth_RW_State_Idle =>
                    o_Eth_CS     <= '1';
                    o_Eth_WR     <= '1';
                    o_Eth_RD     <= '1';
                    --s_W_RD_WRB     <= 'Z';
                --    Eth_RD <= '1';
                    s_W_DATA_In_Des_Rdy <= '0';
                    s_W_DATA_Out_Des_Done <= '0';
                    
                --    s_W_ADDR        <= (others => 'Z');
                --    s_W_DATA_Out    <= (others => 'Z');
                --    io_Data <= (others => 'Z');
                    if s_WriteTrig = '1' then
                    
                        s_W_RD_WRB     <= '0';
                        o_Eth_CS     <= '0';
                        s_W_ADDR        <= s_W_ADDR_Des;
                        s_W_DATA_Out    <= s_W_DATA_Out_Des;
                        s_Eth_RW_State <= c_Eth_RW_State_W1;
                    
                    
                    
                    
--                        s_W_RD_WRB     <= '0';
--                        o_Eth_CS     <= '0';
--                        s_W_ADDR        <= s_W_ADDR_Des;
--                        io_Data    <= s_W_DATA_Out_Des;
--                        s_Eth_RW_State <= c_Eth_RW_State_W1;
                    elsif s_ReadTrig = '1' then
--                        s_W_RD_WRB     <= '1';
--                        o_Eth_CS     <= '0';
--                        s_W_ADDR        <= s_W_ADDR_Des;
--                        o_Eth_RD     <= '0';
--
--                        s_Eth_RW_State <= c_Eth_RW_State_R1;

                --        Eth_RD     <= '0';
                        s_W_RD_WRB     <= '1';
                        o_Eth_CS     <= '0';
                        s_W_ADDR        <= s_W_ADDR_Des;
                        o_Eth_RD     <= '0';
                        s_Eth_RW_State <= c_Eth_RW_State_R1;
                    end if;

                when c_Eth_RW_State_W1 =>    
                    o_Eth_WR <= '0';
                --    Eth_RD <= '0';
                    s_W_DATA_Out_Des_Done <= '1';
                    s_Eth_RW_State <= c_Eth_RW_State_Idle;
                    
                    
                    

                when c_Eth_RW_State_R1 =>
                    o_Eth_RD     <= '0';
                --    Eth_RD <= '0';
                    
                            
                --        x1(0) <= '1';


--                        
--                    x1(2) <= '1';
--                    s_W_DATA_In_Des_Rdy <= '1';
--                    s_Eth_RW_State <= c_Eth_RW_State_Idle;    
                    s_W_DATA_In_Des    <= s_W_DATA_In;
        --            s_W_DATA_In_Des    <= io_Data;    
                    s_W_DATA_In_Des_Rdy <= '1';
                    s_Eth_RW_State <= c_Eth_RW_State_Idle;
                when others =>
                    s_Eth_RW_State <= c_Eth_RW_State_Idle;

            end case;

        end if;
    end process;


end behavioral;


///////////////////////////////////////////////////////////////////Package



Code:
--
--    Package File Template
--
--    Purpose: This package defines supplemental types, subtypes, 
--         constants, and functions 
--
--   To use any of the example code shown below, uncomment the lines and modify as necessary
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

package AVA6STest_Package is

--------------------------------------------------------------------------

    SUBTYPE SUBTYPE_3Bit IS STD_LOGIC_VECTOR(3 DOWNTO 1);
    TYPE Array_3Bit IS ARRAY (NATURAL RANGE <>) OF SUBTYPE_3Bit;

    SUBTYPE SUBTYPE_5Bit IS STD_LOGIC_VECTOR(5 DOWNTO 1);
    TYPE Array_5Bit IS ARRAY (NATURAL RANGE <>) OF SUBTYPE_5Bit;

    SUBTYPE SUBTYPE_8Bit IS STD_LOGIC_VECTOR(7 DOWNTO 0);
    TYPE Array_8Bit IS ARRAY (NATURAL RANGE <>) OF SUBTYPE_8Bit;

    SUBTYPE SUBTYPE_10Bit IS STD_LOGIC_VECTOR(9 DOWNTO 0);
    TYPE Array_10Bit IS ARRAY (NATURAL RANGE <>) OF SUBTYPE_10Bit;

    SUBTYPE SUBTYPE_32Bit IS STD_LOGIC_VECTOR(31 DOWNTO 0);
    TYPE Array_32Bit IS ARRAY (NATURAL RANGE <>) OF SUBTYPE_32Bit;

--------------------------------------------------------------------------
    CONSTANT c_SPI_WIDTH : INTEGER := 8;
    CONSTANT c_Wiznet_DataWidth : INTEGER := 8;
    CONSTANT c_Wiznet_AddrWidth : INTEGER := 10;
    
    constant c_USB_DataWidth : integer := 8;

    constant c_USB_RAM_DataWidth_R : integer := 8;
    constant c_USB_RD_AddrWidth : integer := 9;
    constant c_USB_RAM_DataWidth_W : integer := 8;
    constant c_USB_WR_AddrWidth : integer := 9;

    constant c_USB_Bulklen_Out : integer := 512;    --in samples
    constant c_USB_Bulklen_In : integer := 512;        --in samples
    
    
--------------------------------------------------------------------------
    signal FREE_SIZE_TX : integer := 0;
    signal S0_TX_FSR     : Array_8Bit(2 downto 0) := (x"00",x"00",x"00");
    signal S0_TX_FSR_v : std_logic_vector (23 downto 0):= (others => '0');
    signal S0_TX_FSR_RD : std_logic := '0';
--------------------------------------------------------------------------    
    constant PACKET_SIZE_TOSEND : integer  := 32*512;--*16bit --2048 bytes
    constant S0_TX_FIFOR      : std_logic_vector (9 downto 0) := "10"&x"2E";
    --constant S0_CR          : std_logic_vector (9 downto 0) := "10"&x"02";
    constant S0_CR_SEND      : std_logic_vector (15 downto 0) := x"0020";
--    constant S0_TX_WRSR        : std_logic_vector (9 downto 0) := "10"&x"20";
--    constant S0_TX_WRSR2    : std_logic_vector (9 downto 0) := "10"&x"22";
    constant S0_TX_WRSIZE    : std_logic_vector (31 downto 0) := CONV_STD_LOGIC_VECTOR(PACKET_SIZE_TOSEND*2,32);--size dade ke gharar aast send shavad dar 32 bit neshan dade mishavad

--------------------------------------------------------------------------    
    constant c_WIZNET_INIT_DATA_LENGTH_WR : integer := 60; -- MAC + IP + SUB + GTW Header + ...
    constant c_WIZNET_INIT_DATA_LENGTH_RD : integer := 2;-- Number of registers to be read
    
    constant c_MAC_SOURCE_ADDRESS     : Array_8Bit(5 downto 0) := (x"00", x"16", x"36", x"DE", x"58", x"F6");        
    constant c_IP_SOURCE_ADDRESS     : Array_8Bit(3 downto 0) := (x"AC", x"10", x"0F", x"15"); -- IP = 192.168.0.20
    constant c_SUB_MASK_ADDRESS     : Array_8Bit(3 downto 0) := (x"FF", x"FF", x"FF", x"00"); -- SUB= 255.255.255.0
    constant c_GATWAY_ADDRESS         : Array_8Bit(3 downto 0) := (x"AC", x"10", x"0F", x"0A"); -- GTW = 192.168.0.1    
--    constant c_IP_SOURCE_ADDRESS     : Array_8Bit(3 downto 0) := (x"C0", x"A8", x"00", x"14"); -- IP = 192.168.0.20
--    constant c_SUB_MASK_ADDRESS     : Array_8Bit(3 downto 0) := (x"FF", x"FF", x"FF", x"00"); -- SUB= 255.255.255.0
--    constant c_GATWAY_ADDRESS         : Array_8Bit(3 downto 0) := (x"C0", x"A8", x"00", x"01"); -- GTW = 192.168.0.1    
    constant c_IP_DESTINATION_ADDRESS     : Array_8Bit(3 downto 0) := (x"AC", x"10", x"0F", x"8E"); -- IP = 192.168.0.20
    
-- Sn_MR = 0x02; /* sets UDP mode */
-- Sn_PORTR = source_port; /* sets source port number */
-- Sn_CR = OPEN;
    constant MTYPER0 : std_logic_vector (7 downto 0) := x"FF";
    constant MTYPER1 : std_logic_vector (7 downto 0) := x"00";
    
    constant TMSR0 : std_logic_vector (7 downto 0) := x"08";
    constant TMSR1 : std_logic_vector (7 downto 0) := x"08";
    constant TMSR2 : std_logic_vector (7 downto 0) := x"08";
    constant TMSR3 : std_logic_vector (7 downto 0) := x"08";
    constant TMSR4 : std_logic_vector (7 downto 0) := x"08";
    constant TMSR5 : std_logic_vector (7 downto 0) := x"08";
    constant TMSR6 : std_logic_vector (7 downto 0) := x"08";
    constant TMSR7 : std_logic_vector (7 downto 0) := x"08";

    constant RMSR0 : std_logic_vector (7 downto 0) := x"08";
    constant RMSR1 : std_logic_vector (7 downto 0) := x"08";
    constant RMSR2 : std_logic_vector (7 downto 0) := x"08";
    constant RMSR3 : std_logic_vector (7 downto 0) := x"08";
    constant RMSR4 : std_logic_vector (7 downto 0) := x"08";
    constant RMSR5 : std_logic_vector (7 downto 0) := x"08";
    constant RMSR6 : std_logic_vector (7 downto 0) := x"08";
    constant RMSR7 : std_logic_vector (7 downto 0) := x"08";
    
    
    constant c_S0_MR1      : std_logic_vector (7 downto 0) := x"02"; -- UDP Mode
    constant c_S0_PORTR0 : std_logic_vector (7 downto 0) := x"13"; 
    constant c_S0_PORTR1 : std_logic_vector (7 downto 0) := x"88"; -- port 5000
    constant C_S0_DPORTR0 :std_logic_vector (7 downto 0) := x"13";
    constant C_S0_DPORTR1 :std_logic_vector (7 downto 0) := x"88";--- Destination Port 5000
    signal S0_CR1         : std_logic_vector (7 downto 0) := x"01"; --open 
    --constant S0_TX_WRSR0 : std_logic_vector (7 downto 0) := x"00";
    constant S0_TX_WRSR1 : std_logic_vector (7 downto 0) := x"00";
    constant S0_TX_WRSR2 : std_logic_vector (7 downto 0) := x"00";
    constant S0_TX_WRSR3 : std_logic_vector (7 downto 0) := x"0A";
    
    signal c_WIZNET_INIT_DATA_WR : Array_8Bit(c_WIZNET_INIT_DATA_LENGTH_WR-1 downto 0) := 
                            ( 
                                -- Source MAC Address
                                c_WIZNET_INIT_DATA_LENGTH_WR-1 =>  c_MAC_SOURCE_ADDRESS(5),
                                c_WIZNET_INIT_DATA_LENGTH_WR-2 =>  c_MAC_SOURCE_ADDRESS(4),
                                c_WIZNET_INIT_DATA_LENGTH_WR-3 =>  c_MAC_SOURCE_ADDRESS(3),
                                c_WIZNET_INIT_DATA_LENGTH_WR-4 =>  c_MAC_SOURCE_ADDRESS(2),
                                c_WIZNET_INIT_DATA_LENGTH_WR-5 =>  c_MAC_SOURCE_ADDRESS(1),
                                c_WIZNET_INIT_DATA_LENGTH_WR-6 =>  c_MAC_SOURCE_ADDRESS(0),
                                                                
                                -- Source IP Address            
                                c_WIZNET_INIT_DATA_LENGTH_WR-7 =>  c_IP_SOURCE_ADDRESS(3),
                                c_WIZNET_INIT_DATA_LENGTH_WR-8 =>  c_IP_SOURCE_ADDRESS(2),
                                c_WIZNET_INIT_DATA_LENGTH_WR-9 =>  c_IP_SOURCE_ADDRESS(1),
                                c_WIZNET_INIT_DATA_LENGTH_WR-10 => c_IP_SOURCE_ADDRESS(0),
                                                                
                                -- SUBNET MASK Address          
                                c_WIZNET_INIT_DATA_LENGTH_WR-11 => c_SUB_MASK_ADDRESS(3),
                                c_WIZNET_INIT_DATA_LENGTH_WR-12 => c_SUB_MASK_ADDRESS(2),
                                c_WIZNET_INIT_DATA_LENGTH_WR-13 => c_SUB_MASK_ADDRESS(1),
                                c_WIZNET_INIT_DATA_LENGTH_WR-14 => c_SUB_MASK_ADDRESS(0),
                                                                
                                -- GATWAY Address               
                                c_WIZNET_INIT_DATA_LENGTH_WR-15 => c_GATWAY_ADDRESS(3),
                                c_WIZNET_INIT_DATA_LENGTH_WR-16 => c_GATWAY_ADDRESS(2),
                                c_WIZNET_INIT_DATA_LENGTH_WR-17 => c_GATWAY_ADDRESS(1),
                                c_WIZNET_INIT_DATA_LENGTH_WR-18 => c_GATWAY_ADDRESS(0),
                                
--                                
                                --TX RX MEMORY
                                
                                
                                c_WIZNET_INIT_DATA_LENGTH_WR-19 => TMSR0,
                                c_WIZNET_INIT_DATA_LENGTH_WR-20 => TMSR1,
                                c_WIZNET_INIT_DATA_LENGTH_WR-21 => TMSR2,
                                c_WIZNET_INIT_DATA_LENGTH_WR-22 => TMSR3,
                                c_WIZNET_INIT_DATA_LENGTH_WR-23 => TMSR4,
                                c_WIZNET_INIT_DATA_LENGTH_WR-24 => TMSR5,
                                c_WIZNET_INIT_DATA_LENGTH_WR-25 => TMSR6,
                                c_WIZNET_INIT_DATA_LENGTH_WR-26 => TMSR7,
                                
                                c_WIZNET_INIT_DATA_LENGTH_WR-27 => RMSR0,
                                c_WIZNET_INIT_DATA_LENGTH_WR-28 => RMSR1,
                                c_WIZNET_INIT_DATA_LENGTH_WR-29 => RMSR2,
                                c_WIZNET_INIT_DATA_LENGTH_WR-30 => RMSR3,
                                c_WIZNET_INIT_DATA_LENGTH_WR-31 => RMSR4,
                                c_WIZNET_INIT_DATA_LENGTH_WR-32 => RMSR5,
                                c_WIZNET_INIT_DATA_LENGTH_WR-33 => RMSR6,
                                c_WIZNET_INIT_DATA_LENGTH_WR-34 => RMSR7,
                                
                                c_WIZNET_INIT_DATA_LENGTH_WR-35 => MTYPER0,
                                c_WIZNET_INIT_DATA_LENGTH_WR-36 => MTYPER1,
                                
                                
                                -- Protocol : UDP
                                c_WIZNET_INIT_DATA_LENGTH_WR-37 => c_S0_MR1,
                                
                                -- PORT Adress
                                c_WIZNET_INIT_DATA_LENGTH_WR-38 => c_S0_PORTR0,
                                c_WIZNET_INIT_DATA_LENGTH_WR-39 => c_S0_PORTR1,
                                
                                c_WIZNET_INIT_DATA_LENGTH_WR-40 => S0_CR1,
                                
                                c_WIZNET_INIT_DATA_LENGTH_WR-41 => c_IP_DESTINATION_ADDRESS(3),
                                c_WIZNET_INIT_DATA_LENGTH_WR-42 => c_IP_DESTINATION_ADDRESS(2),
                                c_WIZNET_INIT_DATA_LENGTH_WR-43 => c_IP_DESTINATION_ADDRESS(1),
                                c_WIZNET_INIT_DATA_LENGTH_WR-44 => c_IP_DESTINATION_ADDRESS(0),
                                c_WIZNET_INIT_DATA_LENGTH_WR-45 => C_S0_DPORTR0,
                                c_WIZNET_INIT_DATA_LENGTH_WR-46 => c_S0_DPORTR1,
                                
                                c_WIZNET_INIT_DATA_LENGTH_WR-47 => S0_TX_WRSR1,
                                c_WIZNET_INIT_DATA_LENGTH_WR-48 => S0_TX_WRSR2,
                                c_WIZNET_INIT_DATA_LENGTH_WR-49 => S0_TX_WRSR3,
                                
                                c_WIZNET_INIT_DATA_LENGTH_WR-50 => x"00",
                                c_WIZNET_INIT_DATA_LENGTH_WR-51 => x"00",
                                c_WIZNET_INIT_DATA_LENGTH_WR-52 => x"00",
                                c_WIZNET_INIT_DATA_LENGTH_WR-53 => x"00",
                                c_WIZNET_INIT_DATA_LENGTH_WR-54 => x"00",
                                c_WIZNET_INIT_DATA_LENGTH_WR-55 => x"00",
                                c_WIZNET_INIT_DATA_LENGTH_WR-56 => x"00",
                                c_WIZNET_INIT_DATA_LENGTH_WR-57 => x"00",
                                c_WIZNET_INIT_DATA_LENGTH_WR-58 => x"00",
                                c_WIZNET_INIT_DATA_LENGTH_WR-59 => x"00",
                                
                                
                                c_WIZNET_INIT_DATA_LENGTH_WR-60 => x"20"
                                --c_WIZNET_INIT_DATA_LENGTH_WR-61 => x"10"
                            );
    
    constant c_WIZNET_INIT_ADDR_WR : Array_10Bit(c_WIZNET_INIT_DATA_LENGTH_WR-1 downto 0) := 
                            ( 
                                -- Source MAC Address
                                c_WIZNET_INIT_DATA_LENGTH_WR-1 => "00"&x"08",
                                c_WIZNET_INIT_DATA_LENGTH_WR-2 => "00"&x"09",
                                c_WIZNET_INIT_DATA_LENGTH_WR-3 => "00"&x"0A",
                                c_WIZNET_INIT_DATA_LENGTH_WR-4 => "00"&x"0B",
                                c_WIZNET_INIT_DATA_LENGTH_WR-5 => "00"&x"0C",
                                c_WIZNET_INIT_DATA_LENGTH_WR-6 => "00"&x"0D",

                                -- Source IP Address
                                c_WIZNET_INIT_DATA_LENGTH_WR-7 => "00"&x"18",
                                c_WIZNET_INIT_DATA_LENGTH_WR-8 => "00"&x"19",
                                c_WIZNET_INIT_DATA_LENGTH_WR-9 => "00"&x"1A",
                                c_WIZNET_INIT_DATA_LENGTH_WR-10 => "00"&x"1B",

                                -- SUBNET MASK Address
                                c_WIZNET_INIT_DATA_LENGTH_WR-11 => "00"&x"14",
                                c_WIZNET_INIT_DATA_LENGTH_WR-12 => "00"&x"15",
                                c_WIZNET_INIT_DATA_LENGTH_WR-13 => "00"&x"16",
                                c_WIZNET_INIT_DATA_LENGTH_WR-14 => "00"&x"17",

                                -- GATWAY Address
                                c_WIZNET_INIT_DATA_LENGTH_WR-15 => "00"&x"10",
                                c_WIZNET_INIT_DATA_LENGTH_WR-16 => "00"&x"11",
                                c_WIZNET_INIT_DATA_LENGTH_WR-17 => "00"&x"12",
                                c_WIZNET_INIT_DATA_LENGTH_WR-18 => "00"&x"13",
                                
--                                --tx rx memory
                                
                                
                                c_WIZNET_INIT_DATA_LENGTH_WR-19 => "00"&x"20",
                                c_WIZNET_INIT_DATA_LENGTH_WR-20 => "00"&x"21",
                                c_WIZNET_INIT_DATA_LENGTH_WR-21 => "00"&x"22",
                                c_WIZNET_INIT_DATA_LENGTH_WR-22 => "00"&x"23",
                                c_WIZNET_INIT_DATA_LENGTH_WR-23 => "00"&x"24",
                                c_WIZNET_INIT_DATA_LENGTH_WR-24 => "00"&x"25",
                                c_WIZNET_INIT_DATA_LENGTH_WR-25 => "00"&x"26",
                                c_WIZNET_INIT_DATA_LENGTH_WR-26 => "00"&x"27",
                                
                                c_WIZNET_INIT_DATA_LENGTH_WR-27 => "00"&x"28",
                                c_WIZNET_INIT_DATA_LENGTH_WR-28 => "00"&x"29",
                                c_WIZNET_INIT_DATA_LENGTH_WR-29 => "00"&x"2A",
                                c_WIZNET_INIT_DATA_LENGTH_WR-30 => "00"&x"2B",
                                c_WIZNET_INIT_DATA_LENGTH_WR-31 => "00"&x"2C",
                                c_WIZNET_INIT_DATA_LENGTH_WR-32 => "00"&x"2D",
                                c_WIZNET_INIT_DATA_LENGTH_WR-33 => "00"&x"2E",
                                c_WIZNET_INIT_DATA_LENGTH_WR-34 => "00"&x"2F",
                                
                                c_WIZNET_INIT_DATA_LENGTH_WR-35 => "00"&x"30",
                                c_WIZNET_INIT_DATA_LENGTH_WR-36 => "00"&x"31",
                                
                                -- MODE register Address
                                c_WIZNET_INIT_DATA_LENGTH_WR-37 => "10"&x"01",
                                
                                -- PORT Adress
                                c_WIZNET_INIT_DATA_LENGTH_WR-38 => "10"&x"0A",
                                c_WIZNET_INIT_DATA_LENGTH_WR-39 => "10"&x"0B",
--                                
                                --Command Register Adress
                                c_WIZNET_INIT_DATA_LENGTH_WR-40 => "10"&x"03",
                                
--                                -- Destination IP Address
                                c_WIZNET_INIT_DATA_LENGTH_WR-41 => "10"&x"14",
                                c_WIZNET_INIT_DATA_LENGTH_WR-42=> "10"&x"15",
                                c_WIZNET_INIT_DATA_LENGTH_WR-43 => "10"&x"16",
                                c_WIZNET_INIT_DATA_LENGTH_WR-44 => "10"&x"17",
                                
                                --Destination PORT Adress
                                c_WIZNET_INIT_DATA_LENGTH_WR-45 => "10"&x"12",
                                c_WIZNET_INIT_DATA_LENGTH_WR-46 => "10"&x"13",
                                
                                c_WIZNET_INIT_DATA_LENGTH_WR-47 => "10"&x"21",
                                c_WIZNET_INIT_DATA_LENGTH_WR-48 => "10"&x"22",
                                c_WIZNET_INIT_DATA_LENGTH_WR-49 => "10"&x"23",
                                
                                c_WIZNET_INIT_DATA_LENGTH_WR-50 => "10"&x"2E",
                                c_WIZNET_INIT_DATA_LENGTH_WR-51 => "10"&x"2F",
                                c_WIZNET_INIT_DATA_LENGTH_WR-52 => "10"&x"2E",
                                c_WIZNET_INIT_DATA_LENGTH_WR-53 => "10"&x"2F",
                                c_WIZNET_INIT_DATA_LENGTH_WR-54 => "10"&x"2E",
                                c_WIZNET_INIT_DATA_LENGTH_WR-55 => "10"&x"2F",
                                c_WIZNET_INIT_DATA_LENGTH_WR-56 => "10"&x"2E",
                                c_WIZNET_INIT_DATA_LENGTH_WR-57 => "10"&x"2F",
                                c_WIZNET_INIT_DATA_LENGTH_WR-58 => "10"&x"2E",
                                c_WIZNET_INIT_DATA_LENGTH_WR-59 => "10"&x"2F",
                                
                                
                                
                        --        Command Register Adress
                                c_WIZNET_INIT_DATA_LENGTH_WR-60 => "10"&x"03"
                                --c_WIZNET_INIT_DATA_LENGTH_WR-61 => "10"&x"03"
                            );        
                            
--------------------------------------------------------------------------
--constant c_WIZNET_INIT_DATA_RD : Array_8Bit(c_WIZNET_INIT_DATA_LENGTH_RD-1 downto 0); --:= 
                        --  (
                                --c_WIZNET_INIT_DATA_LENGTH_RD-1 => x"22"
                         --  );

constant c_WIZNET_INIT_ADDR_RD : Array_10Bit(c_WIZNET_INIT_DATA_LENGTH_RD-1 downto 0) := 
                          (
                                --c_WIZNET_INIT_DATA_LENGTH_RD-1 => "10"&x"09"
                            --    c_WIZNET_INIT_DATA_LENGTH_RD-1 =>      "10"&x"03"
                                --c_WIZNET_INIT_DATA_LENGTH_RD-1 =>      "10"&x"25",
                        --        c_WIZNET_INIT_DATA_LENGTH_RD-1 => "10"&x"03",
                                c_WIZNET_INIT_DATA_LENGTH_RD-1 => "10"&x"25",
                                c_WIZNET_INIT_DATA_LENGTH_RD-2 => "10"&x"26"
--                                c_WIZNET_INIT_DATA_LENGTH_RD-2 =>      "10"&x"26",
                        --        c_WIZNET_INIT_DATA_LENGTH_RD-3 =>      "10"&x"27"
--                                c_WIZNET_INIT_DATA_LENGTH_RD-4 => "10"&x"03"
                                
                           );                            
--------------------------------------------------------------------------
--------------------------------------------------------------------------
    constant s_WiznetState_Idle            : integer := 0;
    constant s_WiznetState_SOF1            : integer := 1;
    constant s_WiznetState_SOF2            : integer := 2;
    constant s_WiznetState_WriteAdd1    : integer := 3;
    constant s_WiznetState_WriteAdd2    : integer := 4;
    constant s_WiznetState_WriteData1    : integer := 5;
    constant s_WiznetState_WriteData2    : integer := 6;
    constant s_WiznetState_WriteWRB        : integer := 7;
    constant s_WiznetState_ReadAdd1        : integer := 8;
    constant s_WiznetState_ReadAdd2        : integer := 9;    
    constant s_WiznetState_ReadData1    : integer := 10;
    constant s_WiznetState_ReadData2    : integer := 11;
    constant s_WiznetState_ReadData3    : integer := 12;
    constant s_WiznetState_ReadData4    : integer := 13;
    constant s_WiznetState_WriteCSB        : integer := 14;
    constant s_WiznetState_DS1            : integer := 15;

    signal   s_WiznetState : integer range 0 to 30:= s_WiznetState_Idle;    
    signal    delay_counter_W_State : integer range 0 to 100 := 0;
---------------------------------------------------------------    

    constant c_Eth_Config_State_Idle            : integer := 0;
    constant c_Eth_Config_State_Config1            : integer := 1;
    constant c_Eth_Config_State_Config2            : integer := 2;
    constant c_Eth_Config_State_End                : integer := 3;
    constant c_Eth_Config_State_Config3            : integer := 4;
    constant c_Eth_Config_State_Config4            : integer := 5;
    constant c_Eth_Config_State_delay            : integer := 6;
    signal   s_Eth_Config_State : integer range 0 to 10:= c_Eth_Config_State_Idle;

---------------------------------------------------------------
    constant c_Eth_RW_State_Idle                : std_logic_vector(1 downto 0) := "00";
    constant c_Eth_RW_State_W1                    : std_logic_vector(1 downto 0) := "01";
    constant c_Eth_RW_State_R1                    : std_logic_vector(1 downto 0) := "10";
    
    signal   s_Eth_RW_State : std_logic_vector(1 downto 0):= c_Eth_RW_State_Idle;

---------------------------------------------------------------    
    signal s_Idle_cnt : integer := 0;
    signal   s_cnt_Wiznet_Config : integer := 0;
    signal   s_Index1 : integer range 0 to c_WIZNET_INIT_DATA_LENGTH_WR-1 := 0;
    signal   s_Index2 : integer range 0 to c_WIZNET_INIT_DATA_LENGTH_RD-1 := 0;
    signal    s_Wiznet_Ini_Reset         : std_logic := '0';    
    signal    s_Wiznet_Init_PLL         : std_logic := '0';    
    signal    s_WriteTrig                 : std_logic := '0';    
    signal    s_ReadTrig                 : std_logic := '0';    
    signal    s_W_DATA_Out_Des_Done    : std_logic := '0';    
    signal    s_W_DATA_In_Des_Rdy         : std_logic := '0';    
    signal    s_Eth_ReConfig             : std_logic := '0';    

    signal   s_W_DATA_In_Des         : std_logic_vector (c_Wiznet_DataWidth-1 downto 0) := (others => ('0'));
    signal   s_W_DATA_Out_Des         : std_logic_vector (c_Wiznet_DataWidth-1 downto 0) := (others => ('0'));
    signal     s_W_ADDR_Des             : std_logic_vector(c_Wiznet_AddrWidth-1 downto 0):= (others => ('0'));
-----------------------------------------------------------------------------------
    
    signal   s_W_DATA_In  : std_logic_vector (c_Wiznet_DataWidth-1 downto 0) := (others => ('0'));
    signal   s_W_DATA_Out : std_logic_vector (c_Wiznet_DataWidth-1 downto 0) := (others => ('0'));
    signal     s_W_ADDR : std_logic_vector(c_Wiznet_AddrWidth-1 downto 0):= (others => ('0'));
    signal   s_W_RD_WRB    : std_logic := '0';        
    
--------------------------------------------------------------------------
    signal  s_DATA_In   : std_logic_vector (7 downto 0) := (others => ('0'));
    signal  s_DATA_Out  : std_logic_vector (7 downto 0) := (others => ('0'));
    signal    s_interface_type : std_logic := '0';
    signal    s_data_dir : std_logic := '0';    
--------------------------------------------------------------------------


--------------------------------------------------------------------------

end AVA6STest_Package;


Regarding the timing, I used a 10 MHz clock too and nothing changed. I believe with a 10 MHz, there is enough gap between valid data and capture time.
 

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