Binome
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Hi,
I have an input std_logic_vector a. Then I want an output one named r defined (depending on an integer n) as:
r(a'length-1)...r(a'length-n)='0'
r(a'length-1-n)...r(1)=a(a'length-1)...a(n+1)
r(0)=not(a)
I've defined a simple function in a package as:
but when simulating this testbench:
the last 2 bits of r are 'U'.
Please tell me why.
I have an input std_logic_vector a. Then I want an output one named r defined (depending on an integer n) as:
r(a'length-1)...r(a'length-n)='0'
r(a'length-1-n)...r(1)=a(a'length-1)...a(n+1)
r(0)=not(a)
I've defined a simple function in a package as:
Code:
function wit_addr(a : std_logic_vector; n : integer) return std_logic_vector is
variable tmp : std_logic_vector(a'range) := (others => '0');
begin
for i in a'length-n to a'length-1 loop
tmp(i) := '0';
end loop;
for i in 1 to a'length-n-1 loop
tmp(i) := a(i+n);
end loop;
tmp(0) := not(a(n));
return tmp;
end wit_addr;
Code:
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.my_pkg.all;
--------------------------------
entity tb_wit_addr is
end tb_wit_addr;
architecture test of tb_wit_addr is
signal a, r : std_logic_vector(7 downto 0);
begin
p_test : process
begin
a <= "00110011";
r <= wit_addr(a, 6);
wait;
end process;
end test;
Please tell me why.