hcu
Advanced Member level 4
Hello,
I Urge , please don't move this post.
In fpga flow, there is a tool called vivado where one can drag and drop various IPs in to the block design window and connect all the IP's together and hence becomes a SoC .
In asic flow what is the case and the tool used to build soc ? I came across synopsys coreAssembler . upon studying the documentation. I sense, it will do SoC integration and connections between designware IPs. and finally generates RTL for whole SoC .
am i correct ?
I Urge , please don't move this post.
In fpga flow, there is a tool called vivado where one can drag and drop various IPs in to the block design window and connect all the IP's together and hence becomes a SoC .
In asic flow what is the case and the tool used to build soc ? I came across synopsys coreAssembler . upon studying the documentation. I sense, it will do SoC integration and connections between designware IPs. and finally generates RTL for whole SoC .
am i correct ?