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Tool used to design SoC in ASIC flow ?

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hcu

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Hello,

I Urge , please don't move this post.

In fpga flow, there is a tool called vivado where one can drag and drop various IPs in to the block design window and connect all the IP's together and hence becomes a SoC .

In asic flow what is the case and the tool used to build soc ? I came across synopsys coreAssembler . upon studying the documentation. I sense, it will do SoC integration and connections between designware IPs. and finally generates RTL for whole SoC .

am i correct ?
 

Based on this link (https://www.synopsys.com/dw/ipdir.php?ds=core_assembler)
The coreAssembler product is part of the complete set of IP reuse tools available from Synopsys. coreAssembler provides a graphical or command-based environment that guides the designer through the assembly and configuration of an IP-based subsystem. With coreAssembler, designers can easily generate the configured RTL of a subsystem based on the AMBA IP from the DesignWare Library or from IP with an interface that has been packaged for use with coreAssembler with coreBuilder or has an IP-XACT description of the IP to be integrated. IP that has not been packaged for re-use can also be directly imported into the subsystem. With coreAssembler, you can also easily create and package the complete IP-based subsystem for reuse.
Click to expand...
This description sounds just like using the IP Integrator tools in Xilinx's Vivado.
 

Inside the solvnet doc it says
coreAssembler tool provides a infrastructure for building a complete SoC design and verification environment.
it automates the tedious task of connecting , configuring and verifying all of the IP components in the soc.
Click to expand...

keeping this aside, what actually asic people do for soc integration. ? are there any tools present or manually writes top wrapper and includes all modules inside it ??
 

hcu said:
Inside the solvnet doc it says


keeping this aside, what actually asic people do for soc integration. ? are there any tools present or manually writes top wrapper and includes all modules inside it ??
Click to expand...

it's mostly done by hand by an experienced designer. the integration and the floorplan steps are hard to separate, and affect the end results tremendously. you usually need your best guys to do the job.
 

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