First Design with Quartus Prime

Hi guys,

I should design a 4 bit UP/DOWN digital counter with 1/10/100 kHz programmable clock frequency. I have to deal with an internal clock frequency around 50 MHz imposed by the cristal oscillator.
Unfortunately I have to use the Quartus Prime environment and I have some problem in finding the frequency divider and frequency selector blocks (they were available in MAX+Plus II but not in Prime!).
My idea is to use the following a 9-bit counter to obtain 100 kHz from 50 MHz and than a second 4-bit counter to obtain the 10 k and a last 4-bit counter to last 1 kHz. Is this approach fine?
In this way I will have a 3 output cloks and now the problem is how I can create a frequency selector?

Thanks,
Marco

Frequency dividers are no longer available as they are a poor design choice (also, Max+Plus 2 is over 10 years old and very much out of date)

Using clock enables is the best way of doing it. Then the whole design uses the 50Mhz clock, only enabled at the appropriate times (1 in 1000 for 50Khz). You still use a counter as you envisage, but you only have the enable" high when the counter reaches a specific value, rather than specific bits in the counter.

It is much safer as clock dividers generate clocks with logic and can be prone to timing errors (they always were, but modern technology has less much faster logic) People used to use clock dividers when the clocks were much slower and delays were much larger, but it is poor design practice now.

Thanks for your answer! So, you are proposing to replace both frequency divider and frequency selector by the megafunction Clock Control Block (ALTCLKCTRL), right? In this case my project will be simply a Clock Control Block+counter.
I will try it and I will let you now.

Thanks!

Why not just use the 50Mhz clock to generate the appropriate enables? then clock control block not needed.