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Synthesizing a signal as DFF and not DFFS

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oAwad

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Hello all,

I want to instruct the synthesis tool (Design Compiler) to synthesize a certain signal as DFF_X1 but it automatically synthesize it as DFFS_X1 (D-flippflop with active set low), so is there a command to add in my synthesis script ?

Thanks
 

First, the flop choice depends on the coding and which template you have picked. If you are already using one that matches what you want, then the next option is to bar the synthesis tool from using DFFS_X1 with a dont_use command.
 

ThisIsNotSam said:
First, the flop choice depends on the coding and which template you have picked. If you are already using one that matches what you want, then the next option is to bar the synthesis tool from using DFFS_X1 with a dont_use command.
Click to expand...

1) Is there a way to prevent DC from using DFFS with only a specific signal and the rest of the design is not constrained ?

2) If DC by default used DFFS to synthesize a signal, then can I instruct DC to use a normal DFF and may be add an OR gate or something to keep the logic of the circuit correct ?


Thanks !
 

oAwad said:
1) Is there a way to prevent DC from using DFFS with only a specific signal and the rest of the design is not constrained ?

2) If DC by default used DFFS to synthesize a signal, then can I instruct DC to use a normal DFF and may be add an OR gate or something to keep the logic of the circuit correct ?


Thanks !
Click to expand...

1 - I believe the granularity level for the set_dont_use is module level. if you make a module with a single flop, then you could do it by this approach.

2 - just tell the tool not to use DFFS.

3 - you could very easily do a search and replace on the netlist, or could do ECO later. there are so many ways to achieve what you want...
 

How DC synthesize your sequential logic heavily depends on how your RTL is coded.

The following will likely synthesize to a DFFR (DFF with active low reset)
Code: 
always@(posedge clk or negedge rst) 
  if(~rst)  q <= 1'b0;
  else       q <= q_next;

The following will likely synthesize to a DFFS (DFF with active low set)
Code: 
always@(posedge clk or negedge rst) 
  if(~rst)  q <= 1'b1;
  else       q <= q_next;

The following three examples will likely synthesize to a simple DFF, with different combinational/clock_gating circuit on the CLK or D port
Code: 
always@(posedge clk) 
    q <= q_next;

always@(posedge clk) 
  if(~rst)  q <= 1'b0;
               q <= q_next;

always@(posedge clk) 
  if(~rst) q <= 1'b1;
              q <= q_next;

If you really want a specific cell in a certain place, and don't want to give DC the chance to select other cells,
just write the cell out in your RTL code and specify "set_dont_touch" on that cell in your DC script

eg.
Code: 
other RTL code;
other RTL code;
DFF_X1 U_my_dff (.CLK( clk ), .D( q_next ), .Q( q ));
other RTL code;
other RTL code;

in DC script:
set_dont_touch hierarchy/to/module/U_my_dff
 
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