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Size of thermal vias for SMPS PCB

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treez

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Hello,
Do you agree that thermal vias to go in and around the pads of a D2PAK FET on an FR4 PCB should be no more than 0.35mm in diameter? I am speaking of non-solder-filled vias and PCB with 70um copper thickness.
Also, for those thermal vias that are around the D2PAK (ie not underneath it), they should be no closer than 1.7mm to each other (centre to centre of thermal via).
(The product is an offline 150W LED driver.)
 

There is/was a ti.com app note on thermal via size optimisation, but i cant now find it, has it been obseleted?
 

The way I've seen it done is via Finite Element Analysis.

If that is unavailable to you, you could always make some test coupons with different via hole diameters, and with identical load conditions measure the Mosfet's temperature rise.
 

Some fab/assembly houses will put up a fuss if you do any via-in-pad without some sort of fill process. May depend on the plating finish as well. The company I use most often stated that 10mil finished diameter is okay (with HASL finish). Also recommended to not tent those vias on the bottom side, in order to avoid outgassing.
 

Thanks
The company I use most often stated that 10mil finished diameter is okay (with HASL finish). Also recommended to not tent those vias on the bottom side, in order to avoid outgassing.
Thanks,
I presume that they offered a maximum of 0.254mm diameter for vias-in-pads because otherwise the solder paste would wick away down to the bottom layer?
Our bottom layer is currently bare copper which sits on a thermal pad which covers the heatsink. –In this state, I believe that we cannot have vias-in-pads because to do that means you need to cover the vias with solder resist in order to prevent the solder from spilling out over the bottom layer copper?
 

Thanks

Thanks,
I presume that they offered a maximum of 0.254mm diameter for vias-in-pads because otherwise the solder paste would wick away down to the bottom layer?
Our bottom layer is currently bare copper which sits on a thermal pad which covers the heatsink. –In this state, I believe that we cannot have vias-in-pads because to do that means you need to cover the vias with solder resist in order to prevent the solder from spilling out over the bottom layer copper?
Solder can wick through holes of pretty much any diameter. If you need your bottom side to be very planar, then you actually do need filled vias (not necessarily conductive).

When you say "bare copper" do you actually mean no plating at all?
 

When you say "bare copper" do you actually mean no plating at all?
Thanks, i mean copper without solder resist over it.
If you need your bottom side to be very planar, then you actually do need filled vias (not necessarily conductive).
Thanks, do you mean that unfilled vias are slightly "bumpy" and kind of 'break' up above the bottom surface into which they go in to? This mightnt matter too much as there is a slightly squidgy, rubbery thermal pad on which the PCB lies.
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The following ti.com article...
https://www.ti.com/lit/an/snva183b/snva183b.pdf

....tells that thermal vias should be 0.33mm in diameter, however, it does not make it clear whether this is referring to vias under an IC's exposed pad, or vias outside the exposed pad. Do you know?
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I also believe that if you have say a 2oz copper PCB, then the vias do not have that plating thicknes in their "barrel"..is this true?...Is it true that the via plating thickness in the 'barrel' is only about 20um maximum?
 
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I guess the restriction is because (i) several holes with same total area is more efficient in conducting heat than one large hole and (ii) (too) small holes will have too little copper plating on the inside walls to conduct heat effectively.
 
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tells that thermal vias should be 0.33mm in diameter, however, it does not make it clear whether this is referring to vias under an IC's exposed pad, or vias outside the exposed pad. Do you know?

There's no room for thermal vias "outside the exposed pad" with the IC packages addresse by this application note.

Thermal vias beneath a D2PAK pad can be separated by a solder mask strip, there's no need for tenting or restriction regarding possible solder drain. I believe however, that the via size is not so important if you have enough of it. Consider that the PCB has limited lateral (horizontal) thermal conduction anyway.

I also believe that if you have say a 2oz copper PCB, then the vias do not have that plating thicknes in their "barrel"..is this true?...Is it true that the via plating thickness in the 'barrel' is only about 20um maximum?
Depends on the PCB process. Standard 35 µm (1 oz) is using 18 µm copper foil on outer layers, 15 - 20 µm is galvanically plated. Thicker outer layers can have thicker galvanic plating, but don't need necessarily.
 
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