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how to find area, latency, throughput, power in my design?

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Reeyam

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Hi,
My project is design and implementation network on chip based VHDL
I used Xilinx ISE and Synthesizing but i don't know how to find (area, latency, throughput, power) of the design
I get the information in report (design summary, timing summary) in attachment.
So what is meant memory usage ?
Please can anyone help me if he know how finding them?
 

Read Xilinx documentation.
 

I have read it and have no details
 

You have provided no information on the docu you have read and the ISE ver you are using.
Nevertheless if the required docu is not obtained via googling then Xilinx forums is the place to look for.

Page 215: http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/xst.pdf

http://www.xilinx.com/support/answers/55904.html
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_report_device_utilization.htm
http://forums.xilinx.com/t5/Synthesis/meaning-of-parameters-in-ISE-synthesis-report/td-p/502020
 

very thanks
But I did not find how to calculate the latency and throughput in my design
Please if any one have information help me
 

There are a couple of ways:
1. Look at your architecture/code - you can work it out from there
2. Run a simulation and measure it.
3. Measure it on hardware (but the above two are easier)
 

please Can you show me how to find them by architecture/code?
or from simulation? i synthesize the code but no find latency or throughput
 

It's your code - you should be able to work out the pipeline length of the design.
From simulation - stick some data it - count how many clocks to get a result.
This is not something synthesis tools can tell you - as you made the design.
 

thanks

the time it takes (clocks) for the packet to arrive varies according to network congestion
 

thanks

the time it takes (clocks) for the packet to arrive varies according to network congestion

That it a system design question - it has nothing to do with the silicone on the chip. All you can measure is the latency and throughput of your design. The throughput would be theoretical maximum.
 

Ok, but how i can measure them ????

You know what your clock speed is.
You know what the bus width is.
So therefore you can calculate the max bandwidth in bit/s

If you cannot process each word on every clock - then that is a limitation. You should either know this limitation, or you can measure it on hardware.
If this is ethernet - then overload the system with more data than it can handle. Ensure all packets are the same size, then counter the number of packets over a given time window (say 1second) and then you'll have your bandwidth
 

You know what your clock speed is.
You know what the bus width is.
So therefore you can calculate the max bandwidth in bit/s

If you cannot process each word on every clock - then that is a limitation. You should either know this limitation, or you can measure it on hardware.
If this is ethernet - then overload the system with more data than it can handle. Ensure all packets are the same size, then counter the number of packets over a given time window (say 1second) and then you'll have your bandwidth


This method is not useful in my design because the packet time I have varies from one packet to another
The time between sending the packet and reaching the destination, for example 40ns means 4 clock because I have each clock = 10ns
While another packet, time between sending and arriving takes 20 ns means 2 clock

I am very sorry but I need to find an answer
 

I still dont understand what your problem is? these two packets you talk about - are they the same length? if they are different lengths, then it will take different numbers of clocks to complete a packet.
Why cant you calculate the bandwidth?
Whats the bus size? bus size * 100Mhz will give bandwidth in bits/s
 

the length of all packets is 25 bit
my design not based buses
my design network on chip 3x3 mesh based VHDL
5 master and 4 slave
I want to find the specifications of the design in terms of latency, throughput, banwidth and Average energy
 

Latency throughput and bandwidth can only be specified by you, as the designer, as you know the specification of the system (the design tools do not). Energy use has to be measured with an ammeter.
If you do not know how to work them out or measure them, then I suggest there is a weakness in your design documentation.
 

Latency throughput and bandwidth can only be specified by you, as the designer, as you know the specification of the system (the design tools do not). Energy use has to be measured with an ammeter.

This is in the case of a normal network designed in hardware, not on the chip based VHDL
After all thank you very much
 

This is in the case of a normal network designed in hardware, not on the chip based VHDL
After all thank you very much

The analysis is the same in either case, not sure why you think it would be any different (it's a network in both cases). As the packet arrival times are random in nature (based on your previous posts) then the entire analysis is statistical and will end up with a curve of possible latencies through your network on chip. Changes in the loading of the network will affect the latency as will network congestion.

The easiest analysis for worst case latency is to just assume all network resources want the same destination and run a simulation of the system with all ports requesting the same sink port all at the same time. The port that takes the longest to be serviced by the arbiter is the worst case latency in an un-congested network. If there is any buffering in the network then having all the ports filled with data before doing this and seeing when the last packet from the last serviced port is complete will give you the worst case latency in a congested system. Some of these calculations can be very simple if the arbitration is simple and the number of clocks between servicing ports is a consistent value.

If you need a more comprehensive analysis you'll have to resort to determining the service time of the arbiter then use that data as input to something like matlab to analyze the port requests using a statistical approach. I'm not any kind of expert in queuing theory, so I can't help you with setting up such an analysis, but there are a lot of papers written up on that kind of analysis.
 
T=(L/BW+R)∗H

T : latency
L : flits
BW : the link bandwidth
R: the routing delay per hop, (Hop is the basic communication action from switch to switch)
H : the number of hops from the source to the destination node


This is what I was looking for.
Equation to find the latency.

Thanks for trying to help me..
 
The analysis is the same in either case, not sure why you think it would be any different (it's a network in both cases). As the packet arrival times are random in nature (based on your previous posts) then the entire analysis is statistical and will end up with a curve of possible latencies through your network on chip. Changes in the loading of the network will affect the latency as will network congestion.

The easiest analysis for worst case latency is to just assume all network resources want the same destination and run a simulation of the system with all ports requesting the same sink port all at the same time. The port that takes the longest to be serviced by the arbiter is the worst case latency in an un-congested network. If there is any buffering in the network then having all the ports filled with data before doing this and seeing when the last packet from the last serviced port is complete will give you the worst case latency in a congested system. Some of these calculations can be very simple if the arbitration is simple and the number of clocks between servicing ports is a consistent value.

If you need a more comprehensive analysis you'll have to resort to determining the service time of the arbiter then use that data as input to something like matlab to analyze the port requests using a statistical approach. I'm not any kind of expert in queuing theory, so I can't help you with setting up such an analysis, but there are a lot of papers written up on that kind of analysis.

Hello,
I have designed my network on chip in verilog language using xilinx Ise. now I want to evaluate my design with parsec workload?
could you explain to me how can I impose the workload to my network step by step?
thanks in advance...
 

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