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Gyrator implementation of chip inductor

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promach said:
@Ata_sa16

Vc is the voltage node name for V(in) of the following Gm2 circuit block.

Why does Vc drops from around 2.9V to 1.8V ?

View attachment 140634

The exact Gm2 equation as discussed in https://www.reddit.com/r/chipdesign/comments/6j8834/gyrator_implementation_of_chip_inductor/ is as follows:

View attachment 140635
Click to expand...

I dont have any idea.

That is true. You have to write approximate equations in order to understand the circuit behavior not getting stuck in detailed small signal calculations.
in that formula if ro is high, gm4=gm3 and rd=1/gm3 (since ro3 is high), again you will reach Gm=gm1 as i wrote earlier.
 

Regarding transconductance values determination, should I use manual calculation or simulation ? As for transconductance simulation, how would I do it ? in AC small-signal simulation ? I could not find any spice examples on transconductance measurement.
 

for BSIM3v3 NMOS model as in http://sprunge.us/EGHI or below , how do I find out which parameter is the transconductance, gm ?

There is no documentation regarding this at http://ngspice.sourceforge.net/external-documents/models/bsim330_manual.pdf

*model = bsim3v3
*Berkeley Spice Compatibility
* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20
.model N1 NMOS
+Level= 8
+version=3.3.0
+Tnom=27.0
+Acnqsmod=1 elm=3
+Capmod=3
+Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07
+Lint=9.36e-8 Wint=1.47e-7
+Lintnoi=1e-9
+Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612
+Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2
+Nlx= 3.52291E-08 W0= 1.163e-6
+K3b= 2.233
+Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11
+Rdsw= 650 U0= 388.3203 wr=1
+A0= .3496967 Ags=.1 B0=0.546 B1= 1
+Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213
+Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9
+Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04
+Cdsc=-2.147181E-05
+Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0
+Cdscd = 0 Prwg = 0
+Eta0= 1.0281729E-02 Etab=-5.042203E-03
+Dsub= .31871233
+Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03
+Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -.234
+Pvag= 0 delta=0.01
+ Wl = 0 Ww = -1.420242E-09 Wwl = 0
+ Wln = 0 Wwn = .2613948 Ll = 1.300902E-10
+ Lw = 0 Lwl = 0 Lln = .316394
+ Lwn = 0
+kt1=-.3 kt2=-.051
+At= 22400
+Ute=-1.48
+Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10
+Kt1l=0 Kt1=-0.1 Prt=764.3
Click to expand...
 

how do I find out which parameter is the transconductance, gm ?
Click to expand...
None of it particularly. As you know, gm is operation point dependent, the actual circuit operation point and many of the listed level 8 model parameters affect gm.
 

@FvM

However, the mosfets are not in saturation all the time since the input to the CMOS inverter is a sinusoidal wave as shown below:

Transient2_CL_0p07pF.png
 

One guy told me that

"gm is the point behind the y-axis where the lines in saturation meets if you extrapolate them through the linear region when you sweep vds for stepping vgs"
Click to expand...

I could not understand his statement at all.
Do you guys have any insights ?
 

promach said:
@FvM

However, the mosfets are not in saturation all the time since the input to the CMOS inverter is a sinusoidal wave as shown below:

View attachment 140696
Click to expand...

you are applying large signal !

When you apply large signal to your inverter, it wont behave like a gm-cell. It will act like a digital gate.

If your inverter has VDD and GND you should apply Vin=VDD/2 + Vac.sin(wt) and Vac should be small signal.

when your inputs rises to 3 volts PMOS transistor turns off you should not let them (NMOS and PMOS turn off).

so your amplitude should be max vth (Nmos) < Vin < VDD-vth(pmos) and also careful about output swing as well vdsat (nmos) < Vout < VDD-Vdsat(pmos) in order to be sure that both transistors and
operating at saturation

Example: VDD=3 and GND , vth=0.5, Vdsat=0.2

0.5 < Vin < 2.5 and 0.2 < vout < 2.8

Again I suggest you to read some reference books like Behzad Razavi's CMOS before designing these kind of circuitry.

you need to learn about fundamental CMOS design methods and concepts.
 
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    FvM

    FvM

    Points: 2
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@Ata_sa16:

I do not apply those large signal into the CMOS inverter as stimuli myself.

I am probing the input voltage node of the CMOS inverter.

frequency_trap.png
 

**broken link removed**

Amplitude of sine wave = 1V
 

promach said:
**broken link removed**

Amplitude of sine wave = 1V
Click to expand...

"I do not apply those large signal into the CMOS inverter as stimuli myself.

I am probing the input voltage node of the CMOS inverter."

You do not apply ??? you have 2 volts pick to pick voltage ?!?!? Are you aware of that ?!
 
Last edited:

@Ata_sa16

strange, even with "AC 1m" , I am getting some DC value of about 2V at CMOS inverter input. due to Gm2 circuit block ? I suppose ?

Since Cs is like a DC-blocking capacitor, is it correct to take Cs out, figure out a good bias point, and then implement a suitable bias circuit ?

Screenshot from 2017-08-26 15-32-55.png
 

@Ata_sa16

This is a gyrator made up of two gm-cells (X1 and Gm2 blocks), transforming CL into active inductor.

equivalent inductance value, Leq = CL / [(gm of X1 circuit block)*(gm of Gm2 circuit block)]

Should I simulate the two respective values of overall transconductance of Gm2 and X1 circuit blocks independently or inside the larger circuit below with the presence of Cs and CL ?

Screenshot from 2017-09-02 16-30-03.png
 

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