+ Post New Thread
Results 21 to 40 of 45

6th August 2017, 14:18 #21
 Join Date
 Mar 2016
 Location
 Milky Way Galaxy, 179° 56′ 39.4″
 Posts
 252
 Helped
 31 / 31
 Points
 1,366
 Level
 8
Re: Gyrator implementation of chip inductor
You can observe this on figures you have plotted.
Your gm is constant in green line.
I explained it several times. If you want to have constant and linear Gm for you structure you should use source degeneration.
Don't misunderstand me but I suggest you to read CMOS theory before designing these kind of circuits, it will help you a lot.

9th August 2017, 02:19 #22
 Join Date
 Feb 2016
 Posts
 88
 Helped
 0 / 0
 Points
 624
 Level
 5
Re: Gyrator implementation of chip inductor
Thanks for your advice.
For https://github.com/promach/frequency_trap , I am having problem getting the right AC analysis plot.
Therefore, I went back to Gm2 calculation. I have the following plot, should I use rms value ? Besides, did I do anything wrong elsewhere which I had not noticed yet ?

9th August 2017, 02:44 #23

9th August 2017, 03:13 #24
 Join Date
 Feb 2016
 Posts
 88
 Helped
 0 / 0
 Points
 624
 Level
 5
Re: Gyrator implementation of chip inductor
Yes, the above screenshot is from transient simulation. I am using transient simulation to calculate value of Gm2 because I am not getting the desired AC analysis plot.

9th August 2017, 03:13

9th August 2017, 03:35 #25
 Join Date
 Mar 2016
 Location
 Milky Way Galaxy, 179° 56′ 39.4″
 Posts
 252
 Helped
 31 / 31
 Points
 1,366
 Level
 8
Re: Gyrator implementation of chip inductor
Try to build the whole circuit.
It is hard to do half of it and gm here also depends on frequency.
I cannot explain here, if you want to find gm. You may add a capacitor at the output, and measure the current and then divide it by input AC voltage that would be your gm value.
But you have to know the output capacitance load which is the input capacitance of upper inverted amplifier.

9th August 2017, 16:08 #26
 Join Date
 Feb 2016
 Posts
 88
 Helped
 0 / 0
 Points
 624
 Level
 5
Re: Gyrator implementation of chip inductor
I have already done Gm1, Gm2 all together in the github repo. The screenshot I posted just shown Gm2 circuit block.
1) input capacitance of upper inverted amplifier ? How am I going to determine this ?
2) Why use capacitor C2 at the output for Gm2 value calculation ?

10th August 2017, 03:41 #27
 Join Date
 Mar 2016
 Location
 Milky Way Galaxy, 179° 56′ 39.4″
 Posts
 252
 Helped
 31 / 31
 Points
 1,366
 Level
 8
Re: Gyrator implementation of chip inductor
I did not use CL since transistor input has self capacitance but you may add in order to get different values for Leq.
This Leq has self resonance with parasitic capacitors as you see it occurs at 6 GHz so you have to be away from self resonance as much as you can.
Many things happen here but I did a rough simulation and swept R.
As you see in 2.5 GHz i get different L values.
But here my circuit it is suitable to operate at 2.5 otherwise Real part gets high or negative.
Probably it is narrowband L. I don't have that much experience with active inductors since they are kind of useless because of their high noise.
I wont be able to help you more than this. Good luck.

10th August 2017, 03:41

11th August 2017, 10:32 #28
 Join Date
 Feb 2016
 Posts
 88
 Helped
 0 / 0
 Points
 624
 Level
 5
Re: Gyrator implementation of chip inductor
To other ngsice users:
I am simulating active inductor in https://github.com/promach/frequency_trap
Why Vtest = 2 ?

11th August 2017, 10:50 #29
 Join Date
 Jan 2008
 Location
 Bochum, Germany
 Posts
 40,165
 Helped
 12269 / 12269
 Points
 232,556
 Level
 100
Re: Gyrator implementation of chip inductor
How does the present discussion of Gyrator GHz frequency range relate to the original harmonic trap problem with a center frequency of maximal 100 MHz (1* and 2* PLL fref)?

11th August 2017, 18:10 #30
 Join Date
 Mar 2016
 Location
 Milky Way Galaxy, 179° 56′ 39.4″
 Posts
 252
 Helped
 31 / 31
 Points
 1,366
 Level
 8
Re: Gyrator implementation of chip inductor
I guess when you put inverter it acts like digital gate and it saturates so your output becomes VDD or GND.
We know that inverter can operate as amplifier (If we bias it in VDD/2 so it will have small signal gain) maybe instead of that you can put another gm cell.
   Updated   
you may set up this circuit.
Second GM is negative Be careful !
Leq=2.5 nH
R= almost zero
Perfect high Q inductor
BUT !
As I mentioned previously, this circuit does not have any parasitics so you are not observing self resonance but in real world you wont have these perfect results

11th August 2017, 18:10

12th August 2017, 11:28 #31
 Join Date
 Feb 2016
 Posts
 88
 Helped
 0 / 0
 Points
 624
 Level
 5

12th August 2017, 14:27 #32
 Join Date
 Mar 2016
 Location
 Milky Way Galaxy, 179° 56′ 39.4″
 Posts
 252
 Helped
 31 / 31
 Points
 1,366
 Level
 8
Re: Gyrator implementation of chip inductor
That is right. show me your GM block too.
Instead of tran simulation, set up Sparameter simulation. you are measuring impedance !!
How you measure your impedance with transient analysis ? you have to find phase difference between input current voltage in order to see the imaginary part ! That is hard ! Dont forget you are measuring L and R not only R.
100% you have biasing problem here. you have to see the Dc operation points of your circuit before any other simulation

12th August 2017, 16:18 #33
 Join Date
 Feb 2016
 Posts
 88
 Helped
 0 / 0
 Points
 624
 Level
 5

12th August 2017, 18:55 #34
 Join Date
 Mar 2016
 Location
 Milky Way Galaxy, 179° 56′ 39.4″
 Posts
 252
 Helped
 31 / 31
 Points
 1,366
 Level
 8
Re: Gyrator implementation of chip inductor
Remember that:
1) Never start other simulations unless you become sure about DC bias.
2) When you measure impedance you better use sparameter simulation and check Zin.
   Updated   
I found your problem.
You have to understand the working principle of amplifiers and OTAs deeply.
In AC analysis the gate of M5 should be grounded not Vb. It means that you should put a coupling capacitor.
   Updated   
   Updated   
I showed it before but it seems that you are paying attention !

12th August 2017, 21:30 #35

12th August 2017, 23:59 #36
 Join Date
 Mar 2016
 Location
 Milky Way Galaxy, 179° 56′ 39.4″
 Posts
 252
 Helped
 31 / 31
 Points
 1,366
 Level
 8
Re: Gyrator implementation of chip inductor
Yeah I think you are right. For simulation it is not necessary.
But I am sure that circuit has biasing problem.

13th August 2017, 01:57 #37
 Join Date
 Feb 2016
 Posts
 88
 Helped
 0 / 0
 Points
 624
 Level
 5
Re: Gyrator implementation of chip inductor
Strange, when I do .OP analysis, I have
Doing analysis at TEMP = 25.000000 and TNOM = 27.000000
Warning: vtest: no DC value, transient time 0 value used
No. of Data Rows : 1
Should I resimulate in easyeda online simulator so that we all could edit and debug ?Last edited by promach; 13th August 2017 at 02:07.

13th August 2017, 12:12 #38
 Join Date
 Feb 2016
 Posts
 88
 Helped
 0 / 0
 Points
 624
 Level
 5
Re: Gyrator implementation of chip inductor
Any comment about submicron pch and nch model as in https://sourceforge.net/p/ngspice/di...t=25#84f1/a656 ?

18th August 2017, 08:00 #39
 Join Date
 Feb 2016
 Posts
 88
 Helped
 0 / 0
 Points
 624
 Level
 5
Re: Gyrator implementation of chip inductor
I used Berkeley BSIMv3.3 model, but still some nonsense AC plot. I have zero horizontal line plot at AC amplitude of 0V for V(2) , which is the node above Cs
I think I need to debug even further what else is wrong, especially mosfet sizing in Gm2 circuit block.
By the way, how do you intepret .op verbose output such as following:
ngspice 703 > op
Doing analysis at TEMP = 25.000000 and TNOM = 27.000000
Warning: vtest: no DC value, transient time 0 value used
No. of Data Rows : 1
ngspice 704 > print all
v(1) = 2.900000e+00
v(2) = 1.00000e01
v.xu2.vb#branch = 0.000000e+00
vc = 2.368405e+00
vd#branch = 2.08230e03
vdc#branch = 0.000000e+00
vdd = 3.000000e+00
vs#branch = 2.082300e03
vss = 0.000000e+00
vtest#branch = 0.000000e+00
vx = 1.814641e+00
xu2.1 = 2.750664e+00
xu2.3 = 1.370506e+00
xu2.4 = 1.800000e+00
xu2.5 = 1.585891e+00
ngspice 705 >

19th August 2017, 04:49 #40
 Join Date
 Feb 2016
 Posts
 88
 Helped
 0 / 0
 Points
 624
 Level
 5
Re: Gyrator implementation of chip inductor
@Ata_sa16
Vc is the voltage node name for V(in) of the following Gm2 circuit block.
Why does Vc drops from around 2.9V to 1.8V ?
The exact Gm2 equation as discussed in https://www.reddit.com/r/chipdesign/...chip_inductor/ is as follows:

19th August 2017, 04:49
+ Post New Thread
Please login