promach
Advanced Member level 4
I am trying to divide 48MHz into 9600Hz using the following fractional divider.
Why am I getting baud_out period of 104170ns (simulation) instead of 104167ns (calculation) ? How to calculate this 3ns difference ?
Why am I getting baud_out period of 104170ns (simulation) instead of 104167ns (calculation) ? How to calculate this 3ns difference ?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 // credit: Adapted from [url]https://zipcpu.com/blog/2017/06/02/generating-timing.html[/url] module baud_generator(clk, baud_out); // we are obtaining baud_out = 9600bps = clk/5000 where clk = 48MHz input clk; output baud_out; reg ck_stb; reg[31:0] counter = 0; always @(posedge clk) {ck_stb, counter} <= counter + 858993; // (2^32)/5000 ~= 858993 , actual baudrate = 9599.9949bps // baud_out has a period of (1/9599.9949bps) or 104167ns assign baud_out = ck_stb; endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 `timescale 1ps/1ps module baud_generator_tb; reg clk; wire baud_out; baud_generator BG1 ( .clk(clk), .baud_out(baud_out) ); initial begin $dumpfile("baud_generator.vcd"); $dumpvars(0, baud_generator_tb); clk = 0; #1000000000 $finish; end always #10417 clk = !clk; // 48Mhz has a clock period of (20833/2)ps endmodule