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Help needed in Designware IP usage and the DC script commands. ?

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hcu

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Hello,

I infered design ware IP component in the verilog code as,
Code:
module adder (in1,in2,carry_in,sum,carry_out);
	parameter wordlength = 8;
	input [wordlength-1:0] in1,in2;
	input carry_in;
	output [wordlength-1:0] sum;
	output carry_out;

DW01_add #(wordlength)
	U1(in1,in2,carry_in,sum,carry_out);


endmodule

and the part of the script i mentioning here is,

Code:
#source rm_setup/dc_setup.tcl

set TARGET_LIBRARY_FILES "/home/synopsys/DC_LIB/ref/28nmlvt/lib28/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpmbwp35cd3nmlvt_120a/tcbn28hpmbwp35cd3nmlvtff0p88v0c.db"
set target_library $TARGET_LIBRARY_FILES
set link_library "* $target_library * $synthetic_library"
set synthetic_library "/home/synopsys/syn/H-2013.03-SP5/libraries/syn/dw_foundation.sldb"

and the netlist file is
Code:
module adder_DW01_add_0 ( A, B, CI, SUM, CO );
  input [7:0] A;
  input [7:0] B;
  output [7:0] SUM;
  input CI;
  output CO;

  wire   [7:1] carry;

  FA1D0BWP35CD3NMLVT U1_7 ( .A(A[7]), .B(B[7]), .CI(carry[7]), .CO(CO), .S(
        SUM[7]) );
  FA1D0BWP35CD3NMLVT U1_6 ( .A(A[6]), .B(B[6]), .CI(carry[6]), .CO(carry[7]), 
        .S(SUM[6]) );
  FA1D0BWP35CD3NMLVT U1_5 ( .A(A[5]), .B(B[5]), .CI(carry[5]), .CO(carry[6]), 
        .S(SUM[5]) );
  FA1D0BWP35CD3NMLVT U1_4 ( .A(A[4]), .B(B[4]), .CI(carry[4]), .CO(carry[5]), 
        .S(SUM[4]) );
  FA1D0BWP35CD3NMLVT U1_3 ( .A(A[3]), .B(B[3]), .CI(carry[3]), .CO(carry[4]), 
        .S(SUM[3]) );
  FA1D0BWP35CD3NMLVT U1_2 ( .A(A[2]), .B(B[2]), .CI(carry[2]), .CO(carry[3]), 
        .S(SUM[2]) );
  FA1D0BWP35CD3NMLVT U1_1 ( .A(A[1]), .B(B[1]), .CI(carry[1]), .CO(carry[2]), 
        .S(SUM[1]) );
  FA1D0BWP35CD3NMLVT U1_0 ( .A(A[0]), .B(B[0]), .CI(CI), .CO(carry[1]), .S(
        SUM[0]) );
endmodule


module adder ( in1, in2, carry_in, sum, carry_out );
  input [7:0] in1;
  input [7:0] in2;
  output [7:0] sum;
  input carry_in;
  output carry_out;


  adder_DW01_add_0 U1 ( .A(in1), .B(in2), .CI(carry_in), .SUM(sum), .CO(
        carry_out) );
endmodule


1. what exactly dw_foundation.sldb doing here (a small 136 kb file) , I know it is needed to use Designware library? .if i go for complex designs like axi, ahb spi like that. the same line is enough there also ?
2.DW01_add componenet inferring means , just copying a (adder )source of verilog (or) using design Implementation of adder ,if latter is the case, then netlist i shown here shouldn't be consits of tsmc cells ?
3. Is it true that if i opt to use Designware libraries from synopys , i shouldn't use standard cells because designware libraries are already netlist files.?

Overall, any wrong anyhere or wrong thinking. please guide me.
 

Hello,

I infered design ware IP component in the verilog code as,
Code:
module adder (in1,in2,carry_in,sum,carry_out);
	parameter wordlength = 8;
	input [wordlength-1:0] in1,in2;
	input carry_in;
	output [wordlength-1:0] sum;
	output carry_out;

DW01_add #(wordlength)
	U1(in1,in2,carry_in,sum,carry_out);


endmodule

and the part of the script i mentioning here is,

Code:
#source rm_setup/dc_setup.tcl

set TARGET_LIBRARY_FILES "/home/synopsys/DC_LIB/ref/28nmlvt/lib28/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpmbwp35cd3nmlvt_120a/tcbn28hpmbwp35cd3nmlvtff0p88v0c.db"
set target_library $TARGET_LIBRARY_FILES
set link_library "* $target_library * $synthetic_library"
set synthetic_library "/home/synopsys/syn/H-2013.03-SP5/libraries/syn/dw_foundation.sldb"

and the netlist file is
Code:
module adder_DW01_add_0 ( A, B, CI, SUM, CO );
  input [7:0] A;
  input [7:0] B;
  output [7:0] SUM;
  input CI;
  output CO;

  wire   [7:1] carry;

  FA1D0BWP35CD3NMLVT U1_7 ( .A(A[7]), .B(B[7]), .CI(carry[7]), .CO(CO), .S(
        SUM[7]) );
  FA1D0BWP35CD3NMLVT U1_6 ( .A(A[6]), .B(B[6]), .CI(carry[6]), .CO(carry[7]), 
        .S(SUM[6]) );
  FA1D0BWP35CD3NMLVT U1_5 ( .A(A[5]), .B(B[5]), .CI(carry[5]), .CO(carry[6]), 
        .S(SUM[5]) );
  FA1D0BWP35CD3NMLVT U1_4 ( .A(A[4]), .B(B[4]), .CI(carry[4]), .CO(carry[5]), 
        .S(SUM[4]) );
  FA1D0BWP35CD3NMLVT U1_3 ( .A(A[3]), .B(B[3]), .CI(carry[3]), .CO(carry[4]), 
        .S(SUM[3]) );
  FA1D0BWP35CD3NMLVT U1_2 ( .A(A[2]), .B(B[2]), .CI(carry[2]), .CO(carry[3]), 
        .S(SUM[2]) );
  FA1D0BWP35CD3NMLVT U1_1 ( .A(A[1]), .B(B[1]), .CI(carry[1]), .CO(carry[2]), 
        .S(SUM[1]) );
  FA1D0BWP35CD3NMLVT U1_0 ( .A(A[0]), .B(B[0]), .CI(CI), .CO(carry[1]), .S(
        SUM[0]) );
endmodule


module adder ( in1, in2, carry_in, sum, carry_out );
  input [7:0] in1;
  input [7:0] in2;
  output [7:0] sum;
  input carry_in;
  output carry_out;


  adder_DW01_add_0 U1 ( .A(in1), .B(in2), .CI(carry_in), .SUM(sum), .CO(
        carry_out) );
endmodule


1. what exactly dw_foundation.sldb doing here (a small 136 kb file) , I know it is needed to use Designware library? .if i go for complex designs like axi, ahb spi like that. the same line is enough there also ?
2.DW01_add componenet inferring means , just copying a (adder )source of verilog (or) using design Implementation of adder ,if latter is the case, then netlist i shown here shouldn't be consits of tsmc cells ?
3. Is it true that if i opt to use Designware libraries from synopys , i shouldn't use standard cells because designware libraries are already netlist files.?

Overall, any wrong anyhere or wrong thinking. please guide me.

I found some .mr and .syn files in the installation directory. are they useful in my case ?
 

Hello,

I infered design ware IP component in the verilog code as,
Code:
module adder (in1,in2,carry_in,sum,carry_out);
	parameter wordlength = 8;
	input [wordlength-1:0] in1,in2;
	input carry_in;
	output [wordlength-1:0] sum;
	output carry_out;

DW01_add #(wordlength)
	U1(in1,in2,carry_in,sum,carry_out);


endmodule

and the part of the script i mentioning here is,

Code:
#source rm_setup/dc_setup.tcl

set TARGET_LIBRARY_FILES "/home/synopsys/DC_LIB/ref/28nmlvt/lib28/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpmbwp35cd3nmlvt_120a/tcbn28hpmbwp35cd3nmlvtff0p88v0c.db"
set target_library $TARGET_LIBRARY_FILES
set link_library "* $target_library * $synthetic_library"
set synthetic_library "/home/synopsys/syn/H-2013.03-SP5/libraries/syn/dw_foundation.sldb"

and the netlist file is
Code:
module adder_DW01_add_0 ( A, B, CI, SUM, CO );
  input [7:0] A;
  input [7:0] B;
  output [7:0] SUM;
  input CI;
  output CO;

  wire   [7:1] carry;

  FA1D0BWP35CD3NMLVT U1_7 ( .A(A[7]), .B(B[7]), .CI(carry[7]), .CO(CO), .S(
        SUM[7]) );
  FA1D0BWP35CD3NMLVT U1_6 ( .A(A[6]), .B(B[6]), .CI(carry[6]), .CO(carry[7]), 
        .S(SUM[6]) );
  FA1D0BWP35CD3NMLVT U1_5 ( .A(A[5]), .B(B[5]), .CI(carry[5]), .CO(carry[6]), 
        .S(SUM[5]) );
  FA1D0BWP35CD3NMLVT U1_4 ( .A(A[4]), .B(B[4]), .CI(carry[4]), .CO(carry[5]), 
        .S(SUM[4]) );
  FA1D0BWP35CD3NMLVT U1_3 ( .A(A[3]), .B(B[3]), .CI(carry[3]), .CO(carry[4]), 
        .S(SUM[3]) );
  FA1D0BWP35CD3NMLVT U1_2 ( .A(A[2]), .B(B[2]), .CI(carry[2]), .CO(carry[3]), 
        .S(SUM[2]) );
  FA1D0BWP35CD3NMLVT U1_1 ( .A(A[1]), .B(B[1]), .CI(carry[1]), .CO(carry[2]), 
        .S(SUM[1]) );
  FA1D0BWP35CD3NMLVT U1_0 ( .A(A[0]), .B(B[0]), .CI(CI), .CO(carry[1]), .S(
        SUM[0]) );
endmodule


module adder ( in1, in2, carry_in, sum, carry_out );
  input [7:0] in1;
  input [7:0] in2;
  output [7:0] sum;
  input carry_in;
  output carry_out;


  adder_DW01_add_0 U1 ( .A(in1), .B(in2), .CI(carry_in), .SUM(sum), .CO(
        carry_out) );
endmodule


1. what exactly dw_foundation.sldb doing here (a small 136 kb file) , I know it is needed to use Designware library? .if i go for complex designs like axi, ahb spi like that. the same line is enough there also ?
2.DW01_add componenet inferring means , just copying a (adder )source of verilog (or) using design Implementation of adder ,if latter is the case, then netlist i shown here shouldn't be consits of tsmc cells ?
3. Is it true that if i opt to use Designware libraries from synopys , i shouldn't use standard cells because designware libraries are already netlist files.?

Overall, any wrong anyhere or wrong thinking. please guide me.

1 - designware is a collection or architectural implementations of complex arithmetic logic. typically adders and multipliers. if you want to use other IP, you need other IP.
2 - architecture and implementation are not the same thing.
3 - no, of course not. this is backwards.
 

1 - designware is a collection or architectural implementations of complex arithmetic logic. typically adders and multipliers. if you want to use other IP, you need other IP.
2 - architecture and implementation are not the same thing.
3 - no, of course not. this is backwards.

i not understand ur third point.
 

architecture is not implementation. You can't have a carry look ahead adder implemented without standard cells!

U mean to say that DW library contains only implementations and there is no implementation of CARRY LOOK AHEAD ADDER in designware collections. hence standard cells are required to implement.
 

U mean to say that DW library contains only implementations and there is no implementation of CARRY LOOK AHEAD ADDER in designware collections.
Perhaps you want to say : "U mean to say that DW library contains only architecture and there is no implementation of CARRY LOOK AHEAD ADDER in designware collections."

The DW library defines architecture of various units, the design which is described using RTL.
But when you are synth your design (subsequently implementation), standard cell libraries will be used.
 

The DW library defines architecture of various units, the design which is described using RTL.
But when you are synth your design (subsequently implementation), standard cell libraries will be used.

Thanks for ur reply. ! In the installation directory i see both dw_add.v file (plain text of verilog) and dw_add.syn file (unable to open with any text editor). I believe later one is a dw netlist file . so here when i instantiate "dw_add" IP in the code of my first post. what the dc will take either .syn or .v file. if .syn is the case then i shouldn't do synthesis again on the netlist. may be .v might be the case thats why posted netlist file is filled with tsmc cells.

what u say ? sir
 

Thanks for ur reply. ! In the installation directory i see both dw_add.v file (plain text of verilog) and dw_add.syn file (unable to open with any text editor). I believe later one is a dw netlist file . so here when i instantiate "dw_add" IP in the code of my first post. what the dc will take either .syn or .v file. if .syn is the case then i shouldn't do synthesis again on the netlist. may be .v might be the case thats why posted netlist file is filled with tsmc cells.

what u say ? sir

I say you have some reading to do. Seriously, you have misinterpreted every single thing about using DWare. Do you have a more experienced engineer in your group to assist you? Or maybe do some light reading about dware, synthesis, etc.
 

this is first time working on dw. I thought it was a tool initially. later came to know a little. I have no exp engg. please pinpoint where i am going wrong. i have docs , but lacking how practically things move.
 

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