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fan-out 4 metric (fo4)

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hamedtz

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According to paper '' From energy-delay metric to constraints on the design of digital circuit'' Expressed in the text (Design a two-bit Multiplexer): Finla load CL is normalized to CT and referred as equivalent width WL=48 and load equal to 16 minimum symetrical inverters, how does it mean?

what is the relationship between WL=48 and load equal to 16 minimum inverters?

I uploaded the circuit FO4 (load equal to 16 minimum inverters) , please see attechment and tell me is that correct?

i know minimun symmetrical inverter when wp =2*wn,min=2w1 and CT=Cox*Lmin*Wmin
Multiplexer.JPGfo4.JPG
 

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