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how many times can a DRAM cell be written

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layowblue

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I'm curious about the life span for a standard DRAM row or cell.
As we know current flash cells have their genetic life span in term of number of read/write access.
But how about DRAM cells? Is there a guaranteed life span(in term of read/write times) beyond which a given cell is doomed?
I can't find the answer easily via google.

Any comment is welcomed.
 

Hi,

As we know current flash cells have their genetic life span in term of number of read/write access.
I don't think flash life span is influenced by "read" access. It is only "erase/write" access.

DRAM life span is not at all influenced by any access, afaik.

Klaus
 

There's no known wear mechanism in SRAM or DRAM operation.

Did you notice that DRAM is permanently read and written during refresh action without explicitly accessing it?
 

Hi KlausST, I know what you are saying, but considering the fact that read disturb problem indirectly contributes to erase necessity, read also affects the life span.

- - - Updated - - -

Hi FvM, honestly, I don't believe anything will last forever except God... Even a capacitor has its lifespan.
But if you meant to say that the access frequency is generally not the bottleneck of a DRAM's lifespan, I would take it.
Did you mean it?
 

Hi FvM, honestly, I don't believe anything will last forever except God... Even a capacitor has its lifespan.
But if you meant to say that the access frequency is generally not the bottleneck of a DRAM's lifespan, I would take it.
Did you mean it?
No, FvM stated exactly what has been reported by studies on DRAM technology, there is no known change in the memory cell of a DRAM no mater how may reads and writes are done to the memory cell. Read/write 1 time or 1,000,000,000,000,000,000,000,000 times and the cell will still be the same.

You seem to be convinced that there is a wear mechanism in DRAM and won't accept an accurate answer, that doesn't fit your preconceived belief then why did you bother asking the question in the first place? Maybe you think aging is the same thing as memory cell wear? Aging only takes applying power to the device, you don't even need to read/write to the memory cells for the device for it to eventually fail. Just applying power puts stress on the device's junctions with the increase in temperature, which can help cause metal migration, an other low level physical effects, that have nothing to do with read/write wear.

Flash suffers from read/write wear because physical changes occur on the die and the failure mechanism is due to (eventually after multiple P/E cycles) not being able to change the charge stored in the floating gate.
 

Thanks for the reply anyway. I was just trying to get information confirmed. Your reply indirectly confirms it.:)
No, FvM stated exactly what has been reported by studies on DRAM technology, there is no known change in the memory cell of a DRAM no mater how may reads and writes are done to the memory cell. Read/write 1 time or 1,000,000,000,000,000,000,000,000 times and the cell will still be the same.

You seem to be convinced that there is a wear mechanism in DRAM and won't accept an accurate answer, that doesn't fit your preconceived belief then why did you bother asking the question in the first place? Maybe you think aging is the same thing as memory cell wear? Aging only takes applying power to the device, you don't even need to read/write to the memory cells for the device for it to eventually fail. Just applying power puts stress on the device's junctions with the increase in temperature, which can help cause metal migration, an other low level physical effects, that have nothing to do with read/write wear.

Flash suffers from read/write wear because physical changes occur on the die and the failure mechanism is due to (eventually after multiple P/E cycles) not being able to change the charge stored in the floating gate.
 

FvM also pointed out that DRAM needs refreshing every few mS so either internally or externally, every row or column of the DRAM array is read and rewritten continuously around 250 times every second, even if you are not performing a read or write operation between the device to outside circuitry.

Brian.
 

Every piece of every circuit has wearout mechanisms.
Metal and contacts will fail. Dielectrics will wear out.
But the key is quantitative. These things, normal to
every CMOS circuit since the primordial '70s, are all
engineered to death and not a problem (until some
bright type decides the die cost can be reduced by
a penny, if they cheat just a little more on metal
linewidth, because who really runs the part at 85C
forever?). You have to know the "use model" and
the engineering values for the part. It -could- be
made more reliable than anyone alive today, can
ever worry about. "Could", and "did, being two
quite different things. Maybe they shrunk the
cell 20% by upping the oxide field stress by 30%.
It happens. So does a lot shot 10% thin, before
SPC closes the loop. Now you're at 44% more.
Hope somebody did the reliability work and didn't
outsource it to some "use the usual Ea numbers and
grind out a report, no need to tie up all those ovens
on a test-to-fail" shop.

EEPROM, flash, etc. all work by the same principle
that gives you hot carrier drifts and dielectric wearout.
The critical cells violate the same rules that the
functional circuitry obeys. The trades between read
retention time, write cycle endurance, and the voltage
needed to program the cell, are widely varying. They
will embody what the manufacturer thinks they know
about the customer's acceptable level of reliability
and how they plan (en masse) to use the part. If you
are not with the herd, best pay attention.

DRAM capacitors are only as good as someone thought
they needed to be.
 

Hi,

Hi KlausST, I know what you are saying, but considering the fact that read disturb problem indirectly contributes to erase necessity, read also affects the life span.

I don't agree. You may read a memory without erasing it as often as you like.
A read doesn't need an erase.

Klaus
 

last forever except God... Even a capacitor has its lifespan.

It is not clear whether god existed before man OR he will continue to exist after we all are gone...

But that is taking philosophy too far. Yes, theoretically the max life time is of the order of the life of the universe but that is not what we are talking about.

A simple air core capacitor (like the ones used in the tuners of old radio sets) has practically infinite life. Same is true for a resistor or an inductor. Of course you can spoil a capacitor by applying a very high voltage that can cause sparking and damage the electrode. An inductor can be damaged by excessive currrents. A resistor can be damaged by pushing too much power.

Everything has a safe operating region. Any device can fail even within the safe operating region if you can provide a model. The model must tell some idea about how the damage takes place.

You have not proposed any such failure model. God has failed people by not keeping his promises- but everything can be perhaps explained away.

Last week my pen drive failed in Germany where I was to give a talk. But it came back to life (at home). I can safely blame it only to God action (or inaction).

Many times failure modes are only described on a statistical basis and that does not need the underlying mechanism.
 

Thank you all for the great input. I learned a lot.
The takeaway is: DRAM cell lifespan is generally not a concern as the bottle neck of the device lifespan in normal operation mode.
And don't discuss philosophy here...
 

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