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Voltage Dependent Metal Spacing DRC coding

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Sanketp20

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Hi all,

Is there any way to code DRC for voltage dependant metal spacing DRC checks ?
I know there are tools available for this, like Calibre RealTIme etc. But without spending money on those additional tools, is there any way to do it using basic calibre tools? I have Calibre nmDRC
Given that I have XML file available which contains all Min Max voltages on NETS in layout.

Please help. I really appreciate your guiedence !!

Regards,
Sam
 

A DRC compatible obvious method would be to use auxiliary layer(s) for different voltage classes. For 2 voltage classes (e.g. LV & HV) you'd need just 1 auxiliary layer: copy all (e.g.) HV metal to this auxiliary layer and use the DRC "AND" combination to differentiate between LV & HV spacing.
 

Thank you for your response.

I can follow your recommendation if my DRC is dependent on voltage on NET. But my DRC is dependent on potential differnece between nets. The logic is as following.
Example :
If Potential Difference between two metal1 nets is >=3V then spacing is 3um and if Potential Difference between two metal1 nets is <= 2.99V then spacing is 2um. So I want to find potential difference between neighboring metal layers and based on that I will decide spacing from that metal layer.
 

You probably don't have a static design: this would mean you'd have to find a worst case simulation concerning net voltages (or determine these min. and max. net voltages manually). Then you'd have to write a SKILL program, which assigns these min. and max. net voltage values as properties to the respective nets, then one more SKILL routine, which e.g. creates a new layer structure for layer_net_difference >=3V . Then, standard DRC rules with a logical AND combination can decide on the nets' spacing.

I don't know if newer DRC programs can already use logical decisions not only based on physical (geometrical) dimensions, but perhaps also on net properties. This would spare the 2nd SKILL program.

Of course only nets on the same layer would be affected - you can't change the spacing between nets on different layers.

For a real design I'd never use such a layout complication, would use a global max. spacing. But I admit, this could be a nice academic task.

Good luck!
 

I'd be making (or using) an alternate metal layer
(call it HVMET1) for all such routes, maybe also
some pin relkated DRC "enablers" on block layouts
to enforce use of HVMETx where sensible. Then
the mask Booleans need to combine HVMET into
the layer generation for each metal.

But at 3V, 2um distance is overkill and how high
are you thinking for "high" voltage? Maybe you
are trying too hard. Certainly not much point in
going past 1um when that's as thick as most of
your ILDs are.
 

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